It's late, I'm tired and visions of Block Diagrams and Schematics are dancing around in my head. |)
I checked out the 74ALS245 function and it looks to be the video buffering mechanism. I neglected to mention that the 8 address bits were not a subset of the address bits heading to the Simms in Bank B. They originate from entirely different pins on MDU. I'm guessing the IIci and IIsi use those eight separate address bits for the buffered DRAM as Vampire VRAM setup in both machines.
If there's a Video Card in the IIsi running the monitor and nothing hooked up to the DA-19 connector on the MoBo at startup, then Bank A is never buffered by the 245s from the main memory bus. Bank A would appear to be contiguous with Bank B and its twelve dedicated addressing lines running from different pins on MDU in Bank A's unbuffered state.
Looks to me like you might have a shot at getting al's 16MB of DRAM ICs to work in Bank A if you aren't using that dratted Vampire Video kluge, uni.
Then again . . . :
I checked out the 74ALS245 function and it looks to be the video buffering mechanism. I neglected to mention that the 8 address bits were not a subset of the address bits heading to the Simms in Bank B. They originate from entirely different pins on MDU. I'm guessing the IIci and IIsi use those eight separate address bits for the buffered DRAM as Vampire VRAM setup in both machines.
If there's a Video Card in the IIsi running the monitor and nothing hooked up to the DA-19 connector on the MoBo at startup, then Bank A is never buffered by the 245s from the main memory bus. Bank A would appear to be contiguous with Bank B and its twelve dedicated addressing lines running from different pins on MDU in Bank A's unbuffered state.
Looks to me like you might have a shot at getting al's 16MB of DRAM ICs to work in Bank A if you aren't using that dratted Vampire Video kluge, uni.
Then again . . . :