Yep, but the way the bank addressing works, they can't both go high at the same time because the Mac and MDU cannot address both banks at once. The OR logic for bank addressing is already built into MDU ASIC to begin with.

Am I incorrect in that observation?

The W/E lines control which DRAM ICs on either 16MB side of the double-banked, double sided 72-pin SIMM will be active and which inactive at that end of the traces.