68060 accelerator cards for Mac: Would you be willing? — #42

Post #42 by Bunsen

Source Forum	68kMLA
Category	68k
Post Date	Sun, 9 Sep 2007 - 23:03
Original URL	https://68kmla.org/bb/threads/68060-accelerator-cards-for-mac-would-you-be-willing.8459/

Post

Interesting thoughts, trag. Here's a few of mine.

/ I know how (in theory) to map out the functions of the GAL chips on an old Daystar accelerator card. / Once we knew all those things, we would (roughly) know how to connect the host Macintosh bus to GLUE logic (probably in an FPGA) / I've done FPGA programming /
So, from my hardware point of view, I think it is doable. It would take a lot of time.

/ when I finish assembling the last few IIfx SIMMs

Ah, so you're that guy. Eeeexcellent.

Coldfire chips / lacking an FPU. So, we either live without an FPU / or....
If we're going to try to implement an FPU in an FPGA, then I'd say we're better off just going all the way back to the emulate the 68030 in an FPGA.

I've added a post to the Applefritter thread, with these thoughts:

For reference, here's a block diagram of the 68040:

At the very minimum / "Bus Controller" / duplicate that in the FPGA. / also provide some hardware to streamline the instruction fetch and write-back stages / The *really* hard part of this is going to be emulating the instruction and data cache units. / If you end up running your cache in software that's going to seriously impact the cycles left over for executing code.

Click to expand...

So would it be possible to combine the "streamline" fetch/write hardware you mention and the pseudo-cache? I mean what you're talking about is essentially a real cache before the pseudo cache if I'm reading this right.

So emu the cache stages on the FPGA, or use physical RAM (DDR perhaps) with a DMA chip as cache, and emulate only the ALU and FPU in software? [ / or in the FPGA]

There seems to be a lot of documentation available for the 68030; I haven't looked for much on the '040 yet. As the cult machines people want to overdrive (eg SE/30) are often '030 based, maybe this is a better target than the '040.

Does the above make some kind of sense? If I'm thinking right, it means breaking up the task further, to the chip subsystem level. Emulate the data and instruction caches in hardware, and only build the ALU and FPU in the FPGA.

Other thoughts:

Use some of the DDR RAM as VRAM and add a VGA controller chip.