BootBug "the ideal tool for debugging boot-time code... " Brigent, Inc. 684 Costigan Circle Milpitas, California 95035-3366 (408) 956-0322 (voice & fax) AppleLink: ScottC Warranty Brigent Incorporated (Brigent) warrants BootBug hardware against defects in material and workmanship for 90 Days from the original purchase date. Brigent shall, at its own expense and option, either repair or replace the defective product during the warranty period, provided that the original purchaser has notified Brigent and, upon inspection by Brigent, Brigent has found the product defective. Purchaser's sole and exclusive remedy hereunder shall be limited to the repair or replacement of the product. Any misuse, abuse, modification, or tampering with serial numbers shall void this warranty. The express warranties set forth herein are in lieu of all other warranties, expressed or implied, including without limitation, any warranties of merchantability or fitness for a particular purpose*. In no event will Brigent be liable to the purchaser for damages, including any lost profits, lost savings or other incidental or consequential damages arising out of the use or inability to use such product even if Brigent has been advised of the possibility of such damages, or for any claim for any other party. In any event, the liability of Brigent shall not exceed the purchase price of the product*. * May not apply in some states. · Table of Contents Introduction .............................................................. 1 What is BootBug? .........................................1 How Does BootBug Work? ............................ .1 About the Manual ......................................... l Notations .....................................................2 Installation ..............................................................3 Using a Macintosh as the TerminaL ...............3 Installing the BootBug Card ..........................3 Connecting the Serial Cable ......................... .4 Installing the Terminal SOftware ..................4 Booting BootBug! ..........................................4 Using Another Computer as the TerminaL .....5 How BootBug Works .................................................6 The Boot Process ............................................6 What BootBug Depends On ...........................7 BootBug Debugging Tips ............................................8 Debugger Trap ...............................................8 Breaking on a Primary Init ............................8 Breaking on a SCSI Driver .............................9 BootBug Command Reference .....................................10 Command Expressions .................................... l0 ATB ..............................................................11 ATC ..............................................................12 ATD .............................................................13 ATSS ............................................................ 14 BA…

EtherTalk™ Interface Card Preliminary Note Final Draft 5{29/87 Apple User Education Copyright© 1987 Apple Computer, Inc. All rights reserved. Ether'Ialk Interface Card Preliminary Note 9 APPLE COMPUTER, INC. This document and the product described in it are copyrighted, with all rights reserved. Under the copyright laws, this document may not be copied, in whole or part, without written consent of Apple Computer. The same proprietary and copyright notices must be affixed to any permitted copies as were affixed to the original. This exception does not allow copies to be made for others, whether or not sold, but all of the material purchased may be sold, given, or loaned to another person. Under the law, copying includes translating into another language or format © Apple Com,Puter, Inc., 1987 20525 Mariam Ave. Cu_pertino, California 95014 (408) 996-1010 Apple, the Apple logo, and AppleTalk are registered trademarks of Apple Computer, Inc. EtherTalk, A/UX, .and Macintosh are trademarks of Apple Computer, Inc. Ethernet is a registered trademark of Xerox Corporation. Nubus is a trademark of Texas Instruments. Tlie information in this document reflects the current state of the product. Every attempt has been made to verify the accuracy of this mformation, however, it is subject to change. Preliminar1 notes are released in this form to provide the development commumty with essential information in order to facilitate work on third-party products. Apple Computer Confulential i May 29, 1987 Etheflalk lnterfaa Card Preliminary Note Table of Contents iii iii 1 1 List of Figures List of Tables Introduction Product Overview 2 3 Where to Find Additional Information Network Architecture, Protocols, and Interfaces EtherTalk Card Media Access Method Media Accessc.d by the EtherTalk Card Operating Systems and Drivers EtherTalk Card Hardware Description 4 4 5 5 7 7 8 9 10 11 12 Local Memory Address Assignments NIC Register Addresses Programming Guidelines Initialization Procedure Receive Buffer Ring Overflow Procedure Packet Transmission Apple Computer Confuiential ii May 29, 1987 EtherTalk Interface Card Preliminary Note List of Figures 3 5 6 7 Figure 1. OSI Layers Figure 2. EtherTalk Card Architecture Figure 3. Hardware Model Figure 4. Address Assignments List of Tables 8 9 Table 1. Page 0 Address Assignments (PSl=O, PSO=O) Table 2. Page 1 Address Assignments (PSl=O, PSO=l) Apple Computer Con[ulential iii May 29, 1987 Ethefl'alk Interface Card Preliminary Note Introduction This document is intended for application developers writing communication software for Local Arca Networks (LANs) using the Institute of Electrical and Electronics Engineers (IEEE) 802.3 standards. The document contains programming information for the EtherTalk Interface CanfTM. It is assumed that programmers developing applications for networking environments arc familiar with the software environment they will use. Some familiarity with LANs is also assume…

r REV. ZONE ECO# APPD REVISION A R1416 PRODUCTION RELEASE A R2162 RECORD CHANGE DATE MT 8-9-90 NOTE: MANUFACTURERS RECEIVING APPLE APPROVED VENDOR STATUS FOR THEIR PRODUCT UNDER THIS PART NUMBER PLEASE NOTE: You mJst not change your part design, materials or manufacturing process from those used for the original samples submitted to and approved by Apple without written approval of Apple. Proposed changes determined by Apple to be significant, will require the manufacturer to submit new samples and/or data for review and approval prior to product shipments to Apple. r -$-E3DIMENSIONS ARE IN MIWMETERS. DIMENSIONS IN BRACKETS [ ) ARE IN INCHF.S. TOLERANCES X.X± ., ... 0.3 [.01] 0.13 [.005] x.xxx ± 0.03 [.001] ;; ANGLEs ± 0.1 or as noted \.. DRAYf M.T. ENG APl'D D.I. /$/ 88 :Xv 88 QA APl'D X.XX± DO NOT SCALE ORAWING .® METRIC // RELEASE D.B. DESIGN CK S.R. MFG APl'D A.A. DESIGNER /a/,,88 .Av 89 // SCALE /'3L 89 MATERIAL/FINISH N01ED AS APPLICABLE NONE SIZE A Apple Computer, Inc. NOTI<ll OP PROPRIETARY PROPl3RTY THE INFORMATION CONrAINED HEREIN IS THE PROPRIETARY PROPllRTY OP APl'Ul CDMPU'JllR, INC. THE POSSESSOR AGREES TO 1lIB FOILOWING: (i) TO MAINTAIN TIIIS DOCUMENT IN CDNFIDENCE (ii) Naf TO REPRODUCE OR COPY IT (iii) Naf TO REVEAL OR PUBLISH IT IN WHOLE OR PART TITLE IC, CUSTOM, TFB2.2 144-QFP DRAWING NUMBER 34380077-A SHT 1~0 ..) 1.0 SCOPE: This specifies the parametric requirements of TFB2.2. The TFB2.2 is designed to interface with NuBus, to sense what monitor is used, and generate the corresponding monitor timing, video RAM timing, control and video data for Color look-up table. It is packaged in a 144 pin plastic square quad flat pack. The TFB2.2 is designed to replace Apple P/N 34350019 (TFB2.0) The main difference between TFB2.2 and TFB2.0 are as follow: 1. TFB2.2 extend the enable outputs of ADS, AD9, AD10, AD11 (pin 49, 50, 51, and 52) by 25 ns. 2. TFB2.2 support the NuBus Block Move Access, it effects /ACK, /TM1, and /TMO (pin 43, 53, and 45). 3. TFB2.2 support 1bit/pxl and 2bit/pxl modes, it presents the correct data on the CA Bus (pin 118-125, 128-135). Note: A copy of TFB2.2 schematic is on file in Documentation for Apple Internal use only. Do not remove the original schematic 062-0071 from Documentation files. VD20 VD2 VD1 VD21 VD22 VDO /TSlE VD23 VD24 VD25 SENSE2 SENSE1 SENSEO VD26 VD27 VD28 VD29 VD30 VD31 PXIN GNO /CBLK /CSYN NSYN /SOEO IHSYN /SOE1 A13 A12 A11 IDOEO IDOE1 sco PXOUT GND VDD GNO VDD /RA.SO A10 /RAS1 IC/ISO /CAS1 GND RAO /JS AB A7 N; A5 A4 A'3 RA1 RA2 RA3 GND /SLOT AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 VDD RA4 RA5 RAB RA7 GND N/ENO FIGURE 1. PIN CONFIGURATION \ #._ SIZE DRAWING •®Apple Computer, lnc..,_____......3_4_3s_o_o1_1_-A_ ______ SCALE SHT 2 OP 30 r 1.1 PIN DESCRIPTION INPUTS PIN NAME PIN# DESCRIPTION /10MO /10M1 /RESET AD(7:0) AD(19:12) /SLOTS EL PXIN SENSE(2:0) VD(31 :0) 46 47 48 72-65 80-73 81 101 1…

3Com Ethernet Card Incomin~ Inspection Verification Dia~nostic Tool. vers. 31 Oct '88 The program ETestTool performs physical link level packet transmission and reception between multiple cards on a single machine. The current version allows for multiple machines to perform this test while sharing the same network. In this way, the collision detection and retransmission functionality is verified. Errors detected by the Network Interface Controller (NIC) are timestamped and reported to the screen display. The current version of ETestTool runs as an MPW tool using MPW 2.0 shell or greater. Due to it's UNIX-like structure, the tool may be easily ported to run under A/UX, if desired. This program only reports the statistics of network activity; there is little interpretation of card "Pass" or "Fail" done by the program. As such, one should be familiar with the NIC documentation in order to interpret many of the subtle problems that may exist on a card. The following errors are timestamped & reported to the Macintosh II screen and can be optionally saved to a disk file: • Card RAM failure • 3Com board rework failure • Slot manager failure • CRC, Frame alignment, FIFO overrun errors • FIFO underrun errors • Missed packets due to buffer overflows • Packets lost without an error status reported on either the transmjtter or receiver NIC / In addition, the following occurrences are tallied: • Total packets sent • Number of packet transmissions lost or corrupted • Average number of retries per packet transmission • Number of packets received with CRC errors and/or frame alignment errors • Number of packets missed due to buffer overflow • Number of FIFO overruns and underruns • Number of excessive collisions, out of window collisions • Number of carrier sense lost & collision detect heatbeat failures • Number of transmission timeouts • Number of multicast packets received (none are currently sent by the program) Startin~ the Verification Test Copy the file named ETestTool into the folder which contains the MPW 2.0 (or greater) Shell application. After double-clicking the MPW shell icon to start that application, select the New menu item from the File menu and name the window as you would like the ETestTool result file to appear. In this new window type the following, being certain to use the enter key at the end: ETestTool The test will automatically search for valid etherTalk cards, and will echo each card's slot number. After checking RAM size and verifying the RAM, the test for the 3Com rework is run. Failures are noted before running the packet transfer test. After the rework test, packets are sent from card to card, and errors are noted as they occur. To get the current error accumulatrion status and to pause, hit the mouse button. Press the mouse button again to continue testing. The cursor will spin a quarter turn for every 125 packets sent. To stop testing, simultaneously press the Command (Apple icon) and the period keys. The results may then be…

YY a CErn -PREeE §9- O10 EUROPEAN ORGANIZATION FOR NUCLEAR RESEARCH 9 & SEP. 1989 DEVELOPING FOR THE MACINTOSH NUBUS B.G. Taylor CERN, Geneva, Switzerland CERN LIBRARIES, GENEVA OMAN CM-P00062891 invited paper presented at the EuroBus 89 Conference, London 4 - 6 September 1989 Gq DEVELOPING FOR THE MACINTOSH NUBUS B.G. Taylor EP Division, CERN, 1211 Geneva 23, Switzerland Abstract This paper presents introductory guidelines for European developers of NuBus electronics modules for the Apple Macintosh II family of personal computers. It is based on experience at CERN in developing MacVEE, which interfaces the Macintosh to multi-crate VMEbus and CAMAC systems for data acquisition in large high-energy physics experiments. 1. Introduction While a collaborative truce is being declared by the major open systems bus-war participants, the personal computer market continues to be stimulated by a spirit of lively competition. After navigating quieter waters for over seven years, NuBus emerged into the turbulent mainstream of personal computing with the launch of the Macintosh IT in March 1987. Prior to its adoption by Apple Computer, the bus was little used outside artificial intelligence workstations by Texas Instruments and Lisp Machine. But as the central architecture of Apple’s growing family of ‘Modular Macintosh’ computers, over 250,000 NuBus systems have now been installed worldwide. Apple Europe revenue for 1988 exceeded $1000M, and Europe is now a substantial market for third-party developers of NuBus products. The Apple NuBus is based on minor adaptations of ANSI/IEEE Standard 1196 [1], a concise 70-page specification published in August 1988. This standard is in turn a development of the Texas Instruments NuBus specification [2] first published in 1983, and ‘NuBus’ is a trademark of Texas Instruments Incorporated. The original NuBus was conceived by C. Terman and S. Ward at the Massachusetts Institute of Technology, and was developed by MIT and Western Digital Corporation between 1979 and 1983. NuBus entered the controversial personal computing world just after full 32-bit microprocessors moved into high-volume production, and as the established industry standard architecture based on the PC/AT bus was showing signs of serious fragmentation. Because of Micro Channel licensing restrictions, board size limitations and compatibility issues, different manufacturers chose to follow the patented MCA and open EISA routes in their PS/2 clones. To add to the diversity, IBM themselves introduced an 80286 version of the PS/2 Model 30 based on the older AT-style bus, but for PC-height cards, while confirming that additional MCA enhancements will be introduced in the new 33 MHz Model 75, presumably using undefined reserved lines in the original specification. Since the formation in April 1988 of NuGroup, the association of NuBus manufacturers and users, many organizations have gathered forces around the alternative NuBus architecture 100…

TFB SPECIFICATION Frame buffer specification for 1 February 1986. comments and questions are encouraged, direct them to Toby Farrand at MIS 22Y x2524. TFB Specification Apple Confidential UPDATES TO THE SPECIFICATION The following is a list of changes made to the frame buffer specification for the 28 June 1985 version of the document. 123456789- Support for the planar color model has been dropped from section 1.3. The frame buffer memory map has been updated in section 2.0. Many of the control register definitions have changed in section 3.0. Several pin definitions have changed in section 4.0. Test mode operation has changed, and is explained in section 4.3. Planar mode accesses have been eliminated. Data transfer cycles are changed in section 5.2. Appendix A has been added to suggest possible configurations using the TFB. Timing information has been added in Appendix B. The following is a list of changes made to the frame buffer specification for the 1 February 1986 version of the document. These changes apply only to the 1.1 version of the TFB. 12345678911 10 - Support for variable depth color has been added to the chip. Support for multiplexed address and data buses has been added to the chip. The speed of the chip has been increased substantially. The bus interface has been simplified. The chip parameter descriptions have been rewritten and elaborated on. The SCI- pin has been eliminated in favor of a pixel clock output pin. The DS- pin has been eliminated in favor of a dedicated test mode pin. The definitions and timing of the WEN and CMA buses have been changed. All of the figures and diagrams have been updated. Several configuration paramenter have been added. The appendicies have been updated. 1 February 1986 1 Toby Farrand Apple Confidential TFB Specification TABLE OF CONTENTS 1.0 INTRODUCTION 3 1.1 1.2 1.3 3 4 How to Read this Document System Configuration Features 2.0 DATA ORGANIZATION 5 3.0 CONTROL REGISTER DESCRIPTION 5 3.1 3.2 3.3 6 9 3.4 4.0 5.0 System Configuration Parameters Horizontal Timing Parameters Vertical Timing Parameters Initialization Procedure 11 12 SIGNAL DESCRIPTION 12 4.1 4.2 Inputs Outputs 13 15 Bus Operation 17 5.1 5.2 5.3 17 17 18 RAMCycle Data Transfer Cycle Refresh Cycle 6.0 Future Directions 18 6.0 Conclusion 19 Appendix A - Application Note. 20 Appendix B - Electrical Specifications. 24 Appendix C - Pinout and Mechanical Data. 31 1 February 1986 2 Toby Farrand Apple Confidential TFB Specification 1.0 INTRODUCTION One distinguishing characteristic of Apple's computer products is the tight coupling our machines have between their memory and video systems. This tight coupling results in products which have superior graphics in terms of resolution, speed and cost. This architecture's costs are significant,however, as the video refresh circuitry typically consumes between 40-50% of the available bus bandwidth. The demand for increased processor speed, …

RasterOps RGS14188 User's Guide Preliminary REVISION XA 1 11/2/90 JEFF TINGLEY CONFIDENTIAL THIS DOCUMENT IS THE PROPERTY OF RasterOps REPRODUCllON OF THIS · DOCUMENT IS PROHIBITED . November 2, 1990 RGS14188 User's Guide 1.0 Introduction The RGS14188 Frame Buffer Controller (FBC) is a high-performance CMOS device that controls the video display and dynamic memory of a bit-mapped graphics system. Although the RGS14188 was designed to provide control of varying size, multi-port DRAMs (VRAMs) it works equally well with standard DRAMS and is easily interfaced to a variety of CPUs and buses. The principal role of an FBC is to provide an external processor with virtually unlimited access to (video) memory. It eliminates the delays and overhead caused by display update address generation, reloading shift registers, and DRAM refresh. Furthermore, the FBC reduces the amount of hardware needed to interface a RAM array and provides the user with the utmost flexibility. Highly programmable, the RGS14188 supports a broad range of raster-scan display systems with various resolutions and scan rates. Some of the major functions for RGS14188 FBC are: Generates all control signals necessary to control 256K, 1, 2, and 4 Megabyte VRAM devices, as well as those necessary to control conventional DRAMs of the same sizes. Generates the video synchronization and blanking signals necessary to control a CRT monitor. Accommodates processor data paths of arbitrary widths, working equally well with 8-bit to n-bit processors or bus architectures. Supports both interlaced and non-interlaced displays of essentially any display resolution. Automatically generates the special display-update cycles required by VRAM memories to maintain the CRT display. Automatically performs periodic RAM refresh cycles necessary to maintain the data stored. The block Diagram of a typical system using the RGS14188 is shown in Figure 1-1. 2 RGS14188 User's Guide November 2, 1990 CRT Control Signals RasterOps BGS14188 Host Bus Address Bus DRAM VRAM ROM Video Back End DAC Red Green Blue Data Bus Pixel Clock Figure 1-1 Typical System Using the RGS14188 2.0 Pinout and Signal Descriptions A functional drawing of the RGS14188 is given in Figure 2-1 and the pin number assignments are given in Figure 2-2. A description of each signal is given in the following section. The RGS14188 comes in a 120-terminal plastic quad flat package (PQFP). 3 November 2, 1990 RGS14188 User's Guide Address Input:; ( iP (pull down on (J.7..23] Multiplexed Row and Column Addr CASSelects -RAS1 -RAS2 -RAS3 CASStrobes -CASO -CAS1 -CAS2 -CAS3 Column-address Strobe Column-address Strobe Input latch Enable w ~a: -HCS Host Chip Select +HRD/-HWR ~ §::c -DT/-OE 1 Readylrransfer Acknowlege -PMHOLD (4111A) (4mA) Page Mode Hold Data Buffer Output Enable Vertical Blank ::'ASHIF.T 't~ :: :2}· Address Shift Horizontal Blan -BGACK (4mA) +BG Bus Grant Acknowlege Composite Syn< Bus Grant Input C…

United States Patent (19) 11 45 Fitch et al. (54) SELF-CONFIGURING MEMORY MANAGEMENT SYSTEM WITH ON CARD CRCUTRY FOR NON-CONTENTIOUS ALLOCATION OF RESERVED MEMORY SPACE AMONG EXPANSON CARDS (75) Inventors: Jonathan Fitch, Cupertino; Ronald Hochsprung, Saratoga, both of Calif. (73) Assignee: Apple Computer, Inc., Cupertino, Calif. (21) Appl. No.: 25,500 Patent Number: Date of Patent: 4,905,182 Feb. 27, 1990 OTHER PUBLICATIONS Nu Machine Nu Bus Specification; Texas Instruments; Publication No. TI-2242825-0001; 1983. Texas Instruments; Explorer, Publication No. 2537171-0001; Dec., 1985. NuBus-A Simple 32 Bit Backplane Bus P1196 Specifi cation Draft 2.0, (IEEE), Dec. 15th, 1986, This Docu ment is a Draft Specification of the P1196 Working Group of the Microprocessors Standards Committee of IEEE, (pp. 1-60). Primary Examiner-Raulfe B. Zache Assistant Examiner-Malcolm G. Andrews Attorney, Agent, or Firm-Blakely, Sokoloff, Taylor & Zafiman 22) Filed: Mar. 13, 1987 (51) Int. Cl'....................... G06F 13/14; G06F 13/36 (52) U.S. C. ................................. 364/900; 364/935.4; 364/935.44; 364/964.4 (58) Field of Search ........................ 364/200, 900, 421 (56) References Cited U.S. PATENT DOCUMENTS 3,675,083 7/1972. White .................................. 317/101 3,710,324 1/1973 Cohen et al. ......... ... 364/200 3,993,981 1/1976 Cassarino, Jr. et al. ... 364/200 4,000,485 12/1976 Barlow et al. ....... ... 364/200 4,250,563 2/1981 Struger ............. ... 364/900 4,633,402 12/1986 Flinchbaugh ....................... 364/421 FOREIGN PATENT DOCUMENTS 1380776 1/1975 United Kingdom. 2060961 5/1981 United Kingdom . 2101370 1/1983 United Kingdom . 2103397 2/1983 United Kingdom . (57) ABSTRACT A printed circuit board card adapted to fit into a slot and make electrical connections with cooperating ter minals in the slot, the slot being disposed on the main circuit board of a personal computer system, the main circuit board including a CPU, memory, a 32-bit ad dress bus with control signals associated therewith, and input/output circuitry. The slot is coupled to the 32-bit address bus, being substantially a NUBUS bus, and the slot includes distinct identification line means which provide the slot with an identification number (distinct number) in the computer system. The card includes a decoder means which is coupled to the slot to receive the identification number; the decoder means has nem ory reservation means which causes 256 megabytes of memory space to be reserved for the card in the slot, such that, where the slot number is X, the 256 mega bytes of reserved memory space begins at location SX000 0000 and ends at locations SXFFFFFFF. 10 Claims, 7 Drawing Sheets U.S. Patent Feb. 27, 1990 Sheet 1 of 7 4,905,182 5 . ... CPU 3. 3. 7 IAO NTERFACE ( 9 CPU MOTHER BOARD MEMORY 25 U.S. Patent Feb. 27, 1990 Sheet 2 of 7 4,905,182 PHYSICAL ADDRESS MEMORY SPACE $ FFFF SMALL SPACES FFFF SFOOO OOOO $E SUP…

Apple. Macintosh.Coprocessor Platfonn,. Developer's Guide Beta Draft, 29 November 1989 Networking &: Communications Publications Network Integration Group Keith Grigoletto Apple ContldenHal • APPLE COMPUTEll, INC. This manual is copyrighted by Apple, with all rights reserved. Under the copyright laws, this manual may not be ropied, in whole or in part, without the written consent of Apple Computer, Inc. This exception does not allow copies to be made for others, whether or nct sold, but all of the material purchased may be sold, given or lent to another person. Under the law, copying includes translating into another language. (l Apple Computer, Inc., 1987, lses,l~ 20525 Mariani Avenue Cupertino, California 95014 (4re)?)6.1010 Apple, the Apple logo, AppleTaIk, LaserWriter, and Macintosh are registered trademarks of Apple Computer, Inc. AlROSE, Loca1Talk, the Macintosh Coprocessor Platform, and MPW are trademarks of Apple Computer, Inc. ASf and AST-ICP are trademarks of ASr Research, Inc. DEC is a trademark of the Digital Equipment Corporation. Ethernet Is a trademark of 11 NuBus is a trademark of Texas Instruments. Systems Network Architecture (SNA) is a registered trademark of International Business Machines Corpaation. Simultaneously published in the United States and Canada. Contents Figures and tables / xx Preface / xx What you should know How to use this guide Equipment and system requirements Important safety instructions Conventions used in this guide / xx Terminology Part I Getting Started With MCP 1 What Is MOJ? / 1·1 The canponents of MCP / 1-2 The MCP hardware / 1-3 The MCP software / 1-4 AlROSE /1-5 IAlROS! Prep / 1~ Developmental diagnostics / 1~ Developing with MCP / 1-6 Development opportunities and applications / 1-7 Off-loading task processing / 1-8 Parallel processing / 1-8 Interfacing or controlling / 1-8 Data acquisition / 1-8 Intemetworking / 1-8 limitations / 1-9 2 Getting Started / 2-1 Preparing to use MCP / 2-2 Installing the MCP card / 2-2 Installing MCP software / 2-6 Installing the AlROSE Prep driver / 2~ I viii Running a sample program / 2-7 Selecting files for the sample exercise / 2-8 Downloading files to the card / 2-10 Verifying the sample exercise / 2-10 Where do you go from here? / 2-12 iv Contents Part n Software Development / 3 The MCP Software Interface / 3-1 What is A/ROSE? / 3-2 A/ROSE primitives / 3-2 AlROSE utilities / 3-2 AlROSE managers f 3-2 Echo Manager / H InleICard Communications Manager QCCM) / 3-5 Name Mana8er I 3-5 Print Manaser I 3-5 Remote System Manager (RSM) I 3-5 Tuner library and Tuner Manager / 3-6 Trace Manager I 3-6 What is A/ROSE Prep? / 3-7 A/ROSE Prep driver / 3-7 A/ROSE Prep library / 3-8 A/ROSE Prep managers / 3-8 FunC1ions of MCP software / 3-8 Using messages for interprocess communication / 3-9 Message structures I 3-9 Mechanisms for data transfer I 3-13 Message and status codes I 3-14 The dient/server relationship / 3-14 Client and server ruruUns orr …

HaRivar Mercury 24 Specification Revision XA1 January 20, 1993 Jeff Tingley RasterOps Corporation PART # 0002-0499 CONFIDENTIAL Mercury 24 January 20, 1993 1.0 Introduction This document establishes the physical and electrical characteristics for the Mercury 24, The Mercury 24 is a high resolution, graphics display board for the Macintosh computer. The Mercury 24 occupies one NuBus slot in the Macintosh. It is capable of six pixel depths, multiple resolutions, and has a QuickDraw accelerator. The connectors for a MIPS co-processor or DSP based daughter board are also included. A block diagram of the Mercury 24 is shown in Figure 1-1. This document is the property of RasterOps. Reproduction of this document is prohibited. Video System Controller Synes RGS14188 8 (Venus) 3 Latched Address E § oo NuBus Interface $ (Earth) 3 2 NuBus Flash Eprom Le Mercury RGS90392 ColorBoard Data Bus a= [ NuBus Expansion ] } g [Ay 6 5 DRAM Array Display Memory L R-Bus Expansion | (Up to 256 MBytes) 1024 x 1024 x 32 BT9046-110 (4 MBytes) Clock Synthesizer Figure 1-1 Mercury 24 Block Diagram 2.0 Hardware Description 2.1 Features Switchable Resolutions of (Software Selectable stored in EEPROM or Monitor ID Selectable) - 1280 x 1024 (16-bit, 75 Hz Vertical Refresh, Non-interlaced) - 1152 x 870 (75 Hz Vertical Refresh, Non-interlaced) - 1024 x 768 (60,75 Hz Vertical Refresh, Non-interlaced) - 832 x 624 (75 Hz Vertical Refresh, Non-interlaced) - 640 x 870 (75 Hz Vertical Refresh, Non-interlaced) - 640 x 480 (66 Hz Vertical Refresh, Non-interlaced) Confidential Material 2 Mercury 24 January 20, 1993 Pixel Depths of 1, 2, 4, 8, 16, and 24-bits NuBus Block Mode Migst/Slave Compatible ~oe Yam acces) 134.2 Million Color Palette (9 bit DACs) Mercury based QuickDraw Accelerator RS-343 Video Compatible 15-Pin D-Submininature Connector (Same as Apple) Hardware Zoom of 1x, 2x, 3x... to 16x Smooth Pan independent of pixel depth 2.2 Overview The Mercury 24 is a stand alone frame buffer. It can display up to 24-bits per pixel in one of many resolutions. It is capable of integer zoom and implements smooth paning in all bit depths. The DACs are 9-bit instead of 8-bit to allow for gammas up to 2.4 without redundant colors. A Mercury based QuickDraw Accelerator is included for maximum performance. As an added feature, the Mercury 24 also supports an MIPS coprocessor or a DSP based daughter card. 3.0 Technical Data 3.1. Absolute Maximum Ratings Supply Voltage, VCC ......esesssssssesessssessesesssseeeseessesseeeeens 5.25 Volts Operating Ambient Temperature Range ...........:: 0 °C to 60 °C Storage Temperature ..........sscsscseeseees vee -65 °C to 150 °C ICC (Supply Current) 0... cessseesesssssssssssesesssesseseseeseseeeenees 40A @5.25V 3.2 Reference Drawings The following items should be referenced for information on the Mercury 24. Mercury 24 Top Assembly LM 2642 Mercury 24 Schematics 0002-0496-1 1 Mercury 24 PCB Fab 0002-0497 Mercury 24 PCA 0002-0498-10 Mercu…