;-------------------------------------------------------------------
;
; (c) Apple Computer, Inc.	1987
; All rights reserved.
;
;-------------------------------------------------------------------
;
;	File   	: CommROM.a
;	Author 	: Michael Klassen, June 8, 1987.
;	Description : This file contains the data structure definition 
;		    for the MCP Comm Engine card.
;
;-------------------------------------------------------------------
;	Modification History :
;
;	7 March 1988: WHJW:  mods to support multiple ROM vers w/ same source code
;	8 July  1988: WHJW:	 Correctly identified slot resource list entries
;-------------------------------------------------------------------

;*************************************************************
;Constants
;*************************************************************
  
	INCLUDE	'CommDeclr.h'  
	INCLUDE	'Application.h'  
	
	
	
;Include files
	PRINT	OFF
	INCLUDE	'DeclROMEqu.a'	;Declaration ROM EQU's
	INCLUDE	'SlotMgrEqu.a'	;Slot Manager EQU's
	PRINT	ON


CommROM	MAIN
	STRING 	C
				

;===============================================================================
; Power-On test
; The following jsr PowerOn must be the first instruction of code in the ROM.
; PowerOn tests RAM, ROM, & will then call the Vendor Powerup test defined in ApplPoweron.a
;===============================================================================

	IMPORT	PowerOn		;from powerup.a
	
	jsr	PowerOn

;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;		Resource	Directory 
;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;							<ID>	<OFFSET/DATA>	
_sRsrcDir	OSLstEntry  	sRsrc_Board,_sRsrc_Board	;<sRsrc_Board>  <Board sRsrc List offset>
	OSLstEntry	sRsrc_CPU, _sRsrc_CPU 	; defines CPU, MCP architecture
	OSLstEntry	sRsrc_Comm1, _sRsrc_Comm1	;category Communications
	OSLstEntry	sRsrc_Comm2, _sRsrc_Comm2	;category Communications
	OSLstEntry	sRsrc_Comm3, _sRsrc_Comm3	;category Communications
	OSLstEntry	sRsrc_Comm4, _sRsrc_Comm4	;category Communications
	DatLstEntry	EndOfList,0		;<EndOfList>    <0>



;=============================================================
;			sRsrc_Board List
;=============================================================
;						<ID>		<OFFSET/DATA>	
_sRsrc_Board OSLstEntry	sRsrc_Type,_BoardType	;<sRsrc_Type>  <Board Type offset>
	OSLstEntry	sRsrc_Name,_BoardName	;<sRsrc_Name>  <Name of Board offset>
	DatLstEntry	BoardId,CommBoardId		;<BoardId>     <CommBoardId>
	OSLstEntry	PrimaryInit,_sPInitRec	;<PrimaryInit> <_sPInitRec record offset>
	OSLstEntry	VendorInfo,_VendorInfo	;<VendorInfo>  <_VendorInfo record offset>
	DatLstEntry	EndOfList,0		;<EndOfList>    <0>

_BoardType 	DC.W	CatBoard			;Board sResource :	<Category>
		DC.W	TypBoard			;<Type>		
		DC.W	0			;<DrvrSw>	
		DC.W	0			;<DrvrHw>	
_BoardName	DC.L	'Apple 3270/5250 NB'	;Official Name of Board
				
;-------------------------------------------------------------
;			Vendor Info record
;-------------------------------------------------------------
_VendorInfo	OSLstEntry	VendorId,_VendorId	;<VendorId>  <VendorId offset>
		OSLstEntry	RevLevel,_RevLevel	;<RevLevel>  <RevLevel offset>
		OSLstEntry	PartNum,_PartNum	;<PartNum>   <PartNum offset>
		DatLstEntry	EndOfList,0	;<EndOfList>  <0>

_VendorId		DC.L	'Copyright (C) 1988 Apple Computer'	;Vendor Id
_RevLevel		DC.L	'ROM rev. A'		;Revision Level(note new part #)
_PartNum		DC.L	'342-0667 (H) 342-0666 (L)'	;Part Number


;=============================================================
;			sRsrc_CPU List
;=============================================================
;						<ID>		<OFFSET/DATA>	
_sRsrc_CPU OSLstEntry	sRsrc_Type,_CPUType		;<sRsrc_Type>  <Board Type offset>
	OSLstEntry	sRsrc_Name,_CPUName		;<sRsrc_Name>  <Name of Board offset>
;	OSLstEntry	sRsrc_DrvrDir,_ComDrvrDir	;<sRsrc_DrvrDir><Offset to the Driver directory for Comm sResource>
	OSLstEntry  	MinorBaseOS, _MinorBase
	OSLstEntry  	MinorLength, _MinorLength
	OSLstEntry	sRsrc_sMemory, _sRsrc_sMemory	; defines card memory mapping
	DatLstEntry	EndOfList,0		;<EndOfList>    <0>

_CPUType 		DC.W	CatCPU			;Board sResource :	<Category>
		DC.W	Typ68000			;<Type>		
		DC.W	DrSwNotThere		;<DrvrSw>	
		DC.W	DrHwAMCP			;<DrvrHw>	
_CPUName		DC.L	'CPU_68000_none_AppleMCP'	;Name of CPU
				
_MinorBase	DC.L	0			;Offset is 0
_MinorLength	DC.L	$1000000			;memory map length is 16 Meg

;=============================================================
;			_sRsrc_sMemory List
;=============================================================
;						<ID>		<OFFSET/DATA>	
_sRsrc_sMemory OSLstEntry	sRsrc_Type,_sMemoryType	;<sRsrc_Type>  <Board Type offset>
	OSLstEntry	sRsrc_Name,_sMemoryName	;<sRsrc_Name>  <Name of Board offset>
	OSLstEntry  	MinorRAMAddr, _MinorRAMAddr
	OSLstEntry  	MinorROMAddr, _MinorROMAddr
	OSLstEntry  	MinorDeviceAddr, _MinorDeviceAddr
	DatLstEntry	EndOfList,0		;<EndOfList>    <0>

_sMemoryType 	DC.W	CatsMemory		;Board sResource :	<Category>
		DC.W	1			;<Type>	MCP type	
		DC.W	DrSwNotThere		;<DrvrSw>	
		DC.W	DrHwAMCP			;<DrvrHw>	
_sMemoryName	DC.L	'sMemory'			;Name of resource

_MinorRAMAddr 	DC.L	12			;block size in bytes
		DC.L	$400000			;RAM length (Architecture allows up to 4 Meg)
		DC.L	$0			;RAM base offset

_MinorROMAddr 	DC.L	12			;block size in bytes
		DC.L	$10000			;ROM length (Architecture allows 64K)
		DC.L	$FF0000			;ROM base offset

_MinorDeviceAddr 	DC.L	_EndMinorDeviceAddr - _MinorDeviceAddr	; Block size
		DC.L	$400000			;no decode/DTACK I/O interface logic length
		DC.L	$400000			;no decode/DTACK I/O interface logic offset
		DC.L	$200000			;decode/DTACK I/O interface logic length
		DC.L	$800000			;decode/DTACK I/O interface logic offset
		DC.L	$200000			;NuBus control range length
		DC.L	$A00000			;NuBus control range offset
		DC.L	$00000b			;MCP control range length
		DC.L	$C00000			;MCP control range offset
_EndMinorDeviceAddr	EQU	*			; End of block

;-------------------------------------------------------------
;				Driver directory (not used)
;-------------------------------------------------------------
;_ComDrvrDir	OSLstEntry	sMacOS68020,_sMacOS68020	;<sMacOS68020>  <sMacOS68020 offset>
;		DatLstEntry	EndOfList,0		;<EndOfList>  	<0>


;Driver-1 (68020).
;_sMacOS68020	DC.L	_End020Drvr-_sMacOS68020	;Physical Block Size
;		INCLUDE	'ComDrvr.a'		;The Header/Code
;_End020Drvr	EQU		*
		STRING 	C
				

;=============================================================
;			sRsrc_Comm1 List
;=============================================================
;			<ID>		<OFFSET/DATA>	
_sRsrc_Comm1 OSLstEntry 	sRsrc_Type,_CommunicationType1	;<sRsrc_Type>  <Network Type offset>
	OSLstEntry	sRsrc_Name,_CommunicationName1	;<sRsrc_Name>  <Name of Network offset>
	DatLstEntry	sRsrc_HWDevId,1			;hardware device ID
	DatLstEntry	EndOfList,0			;<EndOfList>    <0>

_CommunicationType1 	DC.W	CatCommunication	;Board sResource :	<Category>
		DC.W	Typ3270			;<Type>		
		DC.W	DrSwNotThere		;<DrvrSw>	
		DC.W	DrHwAMCP			;<DrvrHw>	
_CommunicationName1	DC.L	'Communication_3270_none_AppleMCP' 	;Name of resource
;=============================================================
;			sRsrc_Comm2 List
;=============================================================
;			<ID>		<OFFSET/DATA>	
_sRsrc_Comm2 OSLstEntry 	sRsrc_Type,_CommunicationType2	;<sRsrc_Type>  <Network Type offset>
	OSLstEntry	sRsrc_Name,_CommunicationName2	;<sRsrc_Name>  <Name of Network offset>
	DatLstEntry	sRsrc_HWDevId,2			;hardware device ID
	DatLstEntry	EndOfList,0			;<EndOfList>    <0>

_CommunicationType2 	DC.W	CatCommunication	;Board sResource :	<Category>
		DC.W	Typ3270			;<Type>		
		DC.W	DrSwNotThere		;<DrvrSw>	
		DC.W	DrHwA3270_5250		;<DrvrHw>, implies 8344 chip
_CommunicationName2	DC.L	'Communication_3270_none_8344' 	;Name of resource
;=============================================================
;			sRsrc_Comm3 List
;=============================================================
;			<ID>		<OFFSET/DATA>	
_sRsrc_Comm3 OSLstEntry 	sRsrc_Type,_CommunicationType3	;<sRsrc_Type>  <Network Type offset>
	OSLstEntry	sRsrc_Name,_CommunicationName3	;<sRsrc_Name>  <Name of Network offset>
	DatLstEntry	sRsrc_HWDevId,3		;hardware device ID
	DatLstEntry	EndOfList,0		;<EndOfList>    <0>

_CommunicationType3 	DC.W	CatCommunication	;Board sResource :	<Category>
		DC.W	Typ5250			;<Type>		
		DC.W	DrSwNotThere		;<DrvrSw>	
		DC.W	DrHwAMCP			;<DrvrHw>	
_CommunicationName3	DC.L	'Communication_5250_none_AppleMCP' 	;Name of resource

;=============================================================
;			sRsrc_Comm4 List
;=============================================================
;			<ID>		<OFFSET/DATA>	
_sRsrc_Comm4 OSLstEntry 	sRsrc_Type,_CommunicationType4	;<sRsrc_Type>  <Network Type offset>
	OSLstEntry	sRsrc_Name,_CommunicationName4	;<sRsrc_Name>  <Name of Network offset>
	DatLstEntry	sRsrc_HWDevId,4		;hardware device ID
	DatLstEntry	EndOfList,0		;<EndOfList>    <0>

_CommunicationType4 	DC.W	CatCommunication	;Board sResource :	<Category>
		DC.W	Typ5250			;<Type>	5250	
		DC.W	DrSwNotThere		;<DrvrSw>	
		DC.W	DrHwA3270_5250		;<DrvrHw>, implies 8344 chip
_CommunicationName4	DC.L	'Communication_5250_none_8344' 	;Name of resource


; DO NOT ADD ANYTHING BELOW THIS LINE OR THE PRIMARY INIT CODE WILL FAIL!!!


;-------------------------------------------------------------
;			Primary Init Record
;-------------------------------------------------------------
_sPInitRec	DC.L	_EndsPInitRec-_sPInitRec	;Physical Block Size
		INCLUDE	'PrimaryInit.a'		;The Primary Init Header/Code
_EndsPInitRec	EQU		*		;End of block
		STRING 	C

	DC.W	VendID			; unofficial 3270/5250 id
	DC.W	CommID			; unofficial MCP architecture id
;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;			Format/Header Block
;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
	DC.L	(_sRsrcDir-*)**$00FFFFFF	;Offset to sResource directory
	DC.L	ROMSize			;Length of declaration data
	DC.L	0			;CRC {Patched by crcPatch}
	DC.B	ROMRevLevel		;ROM Revision level defined in application.h
	DC.B	AppleFormat		;Format
	DC.L	TestPattern		;Test pattern
	DC.B	0			;Reserved byte
	DC.B	$0F			;ByteLanes: 0000 1111

	ENDP
	END