NuBus Graphics Card Theory of Operations Toby Farrand Advanced Development Group Computer Graphics Lab 12 August 1986 - ! , NuBus Graphics Card Theory of Operations Toby Farrand Updates to the Specification • This specification applies only to the DVT version of the NGC labeled 1.0. • The CLUT register spaces have moved. • No reads of the card's control of status bits are supported. • The configuration ROM is now lK bytes. • A section on debugging of the card has been added. 12August1986 1 Apple Confidential NuBus Graphics Card Theory of Operations Toby Farrand Table of Contents 1.0 2.0 Overview 3 1.1 Features 1.2 -Cost 3 3 Software Interface 4 2.1 Memory Map 2.2 TFB Operation 4 5 2.2.1 TFB Register Values 2.2.2 TFB Initialization 3.0 5 7 Hardware Description 3.1 3.2 3.3 3.4 7 NuBus Interface Timing Generation Frame Buffer Video Output 8 8 8 9 4.0 Schedule 9 5.0 Debugging 9 6.0 Final Board Features 11 7.0 Layout 12 8.0 Schematics 15 9.0 PAL Equations 24 10.0 Timings 27 11.0 Bt453 Specification 29 12 August 1986 2 Apple Confidential NuBus Graphics Card Theory of Operations 1.0 Toby Farrand Overview The NuBus Graphics Card (NGC) is a high performance, flexible and low cost color graphics card for any Apple NuBus based product The card is based on the TFB frame buffer controller chip designed in the Advanced Development Group, and is targeted for introduction with the Milwaukee machine. 1.1 Features The NOC features variable color depth operation of either 1,2,4 or 8 bits per pixel with a color lookup table providing a palette of 16M colors driving 8 bit DACs for each of the ROB channels. The card is capable of generating proper timing for the Milwaukee monitors, or any RS 170 compatible monitor. (This includes such things as analog film recorders and projection TVs.) The board features high performance -- 400ns reads and writes from the NuBus interface. 1.2 Cost The board is expected to cost no more than $110 for the 512K byte version capable of supporting up to 8 bits per pixel color. A cost breakdown is given below: ITEM APPLE PART PART DESCRIPTION NUMBER ---- -------- QUANTITY PER BOARD EST. UNIT COST PART COST PER BOARD ---------------------- ---------- ---------- ----------- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 TFB (Apple Custom) NEC video RAM µPD41264150ns PAL16R4B 15ns PAL PAL 20R6A 25ns PAL Brooktree Bt453 CLUT/DAC Chip 2716 16K EPROM 74F153 Dual 4:1 MUX AM29841 Ten Bit Latch 74F521 Octal Comparator 74F245 Octal Buffer 74FOO QUAD NANO Gate 74F38 QUAD NANO Gate HY5030-100 Tapped Delay Line 12.2727 MHz Oscillator 30.2400 MHz Oscillator 96 Pin NuBus Connector D-Shell 15 pin connector LM385-1.2 Voltage Reference .1 µF Decoupling Capacitor 10µF Bulk Capacitor Ferrite Bead Resistor SIP Pack 10 pin 22 ohm Resistor, 3.3K ohm 5% Resistor, 47K ohm 5% Resistor, 75 ohm 5% PC Board, 4 layer 4" X 13" 1 16 1 1 1 1 1 1 1 14.50 3.00 1.75 1.7…

EtherTalk™ Interface Card Preliminary Note Final Draft 5{29/87 Apple User Education Copyright© 1987 Apple Computer, Inc. All rights reserved. Ether'Ialk Interface Card Preliminary Note 9 APPLE COMPUTER, INC. This document and the product described in it are copyrighted, with all rights reserved. Under the copyright laws, this document may not be copied, in whole or part, without written consent of Apple Computer. The same proprietary and copyright notices must be affixed to any permitted copies as were affixed to the original. This exception does not allow copies to be made for others, whether or not sold, but all of the material purchased may be sold, given, or loaned to another person. Under the law, copying includes translating into another language or format © Apple Com,Puter, Inc., 1987 20525 Mariam Ave. Cu_pertino, California 95014 (408) 996-1010 Apple, the Apple logo, and AppleTalk are registered trademarks of Apple Computer, Inc. EtherTalk, A/UX, .and Macintosh are trademarks of Apple Computer, Inc. Ethernet is a registered trademark of Xerox Corporation. Nubus is a trademark of Texas Instruments. Tlie information in this document reflects the current state of the product. Every attempt has been made to verify the accuracy of this mformation, however, it is subject to change. Preliminar1 notes are released in this form to provide the development commumty with essential information in order to facilitate work on third-party products. Apple Computer Confulential i May 29, 1987 Etheflalk lnterfaa Card Preliminary Note Table of Contents iii iii 1 1 List of Figures List of Tables Introduction Product Overview 2 3 Where to Find Additional Information Network Architecture, Protocols, and Interfaces EtherTalk Card Media Access Method Media Accessc.d by the EtherTalk Card Operating Systems and Drivers EtherTalk Card Hardware Description 4 4 5 5 7 7 8 9 10 11 12 Local Memory Address Assignments NIC Register Addresses Programming Guidelines Initialization Procedure Receive Buffer Ring Overflow Procedure Packet Transmission Apple Computer Confuiential ii May 29, 1987 EtherTalk Interface Card Preliminary Note List of Figures 3 5 6 7 Figure 1. OSI Layers Figure 2. EtherTalk Card Architecture Figure 3. Hardware Model Figure 4. Address Assignments List of Tables 8 9 Table 1. Page 0 Address Assignments (PSl=O, PSO=O) Table 2. Page 1 Address Assignments (PSl=O, PSO=l) Apple Computer Con[ulential iii May 29, 1987 Ethefl'alk Interface Card Preliminary Note Introduction This document is intended for application developers writing communication software for Local Arca Networks (LANs) using the Institute of Electrical and Electronics Engineers (IEEE) 802.3 standards. The document contains programming information for the EtherTalk Interface CanfTM. It is assumed that programmers developing applications for networking environments arc familiar with the software environment they will use. Some familiarity with LANs is also assume…

r REV. ZONE ECO# APPD REVISION A R1416 PRODUCTION RELEASE A R2162 RECORD CHANGE DATE MT 8-9-90 NOTE: MANUFACTURERS RECEIVING APPLE APPROVED VENDOR STATUS FOR THEIR PRODUCT UNDER THIS PART NUMBER PLEASE NOTE: You mJst not change your part design, materials or manufacturing process from those used for the original samples submitted to and approved by Apple without written approval of Apple. Proposed changes determined by Apple to be significant, will require the manufacturer to submit new samples and/or data for review and approval prior to product shipments to Apple. r -$-E3DIMENSIONS ARE IN MIWMETERS. DIMENSIONS IN BRACKETS [ ) ARE IN INCHF.S. TOLERANCES X.X± ., ... 0.3 [.01] 0.13 [.005] x.xxx ± 0.03 [.001] ;; ANGLEs ± 0.1 or as noted \.. DRAYf M.T. ENG APl'D D.I. /$/ 88 :Xv 88 QA APl'D X.XX± DO NOT SCALE ORAWING .® METRIC // RELEASE D.B. DESIGN CK S.R. MFG APl'D A.A. DESIGNER /a/,,88 .Av 89 // SCALE /'3L 89 MATERIAL/FINISH N01ED AS APPLICABLE NONE SIZE A Apple Computer, Inc. NOTI<ll OP PROPRIETARY PROPl3RTY THE INFORMATION CONrAINED HEREIN IS THE PROPRIETARY PROPllRTY OP APl'Ul CDMPU'JllR, INC. THE POSSESSOR AGREES TO 1lIB FOILOWING: (i) TO MAINTAIN TIIIS DOCUMENT IN CDNFIDENCE (ii) Naf TO REPRODUCE OR COPY IT (iii) Naf TO REVEAL OR PUBLISH IT IN WHOLE OR PART TITLE IC, CUSTOM, TFB2.2 144-QFP DRAWING NUMBER 34380077-A SHT 1~0 ..) 1.0 SCOPE: This specifies the parametric requirements of TFB2.2. The TFB2.2 is designed to interface with NuBus, to sense what monitor is used, and generate the corresponding monitor timing, video RAM timing, control and video data for Color look-up table. It is packaged in a 144 pin plastic square quad flat pack. The TFB2.2 is designed to replace Apple P/N 34350019 (TFB2.0) The main difference between TFB2.2 and TFB2.0 are as follow: 1. TFB2.2 extend the enable outputs of ADS, AD9, AD10, AD11 (pin 49, 50, 51, and 52) by 25 ns. 2. TFB2.2 support the NuBus Block Move Access, it effects /ACK, /TM1, and /TMO (pin 43, 53, and 45). 3. TFB2.2 support 1bit/pxl and 2bit/pxl modes, it presents the correct data on the CA Bus (pin 118-125, 128-135). Note: A copy of TFB2.2 schematic is on file in Documentation for Apple Internal use only. Do not remove the original schematic 062-0071 from Documentation files. VD20 VD2 VD1 VD21 VD22 VDO /TSlE VD23 VD24 VD25 SENSE2 SENSE1 SENSEO VD26 VD27 VD28 VD29 VD30 VD31 PXIN GNO /CBLK /CSYN NSYN /SOEO IHSYN /SOE1 A13 A12 A11 IDOEO IDOE1 sco PXOUT GND VDD GNO VDD /RA.SO A10 /RAS1 IC/ISO /CAS1 GND RAO /JS AB A7 N; A5 A4 A'3 RA1 RA2 RA3 GND /SLOT AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 VDD RA4 RA5 RAB RA7 GND N/ENO FIGURE 1. PIN CONFIGURATION \ #._ SIZE DRAWING •®Apple Computer, lnc..,_____......3_4_3s_o_o1_1_-A_ ______ SCALE SHT 2 OP 30 r 1.1 PIN DESCRIPTION INPUTS PIN NAME PIN# DESCRIPTION /10MO /10M1 /RESET AD(7:0) AD(19:12) /SLOTS EL PXIN SENSE(2:0) VD(31 :0) 46 47 48 72-65 80-73 81 101 1…

3Com Ethernet Card Incomin~ Inspection Verification Dia~nostic Tool. vers. 31 Oct '88 The program ETestTool performs physical link level packet transmission and reception between multiple cards on a single machine. The current version allows for multiple machines to perform this test while sharing the same network. In this way, the collision detection and retransmission functionality is verified. Errors detected by the Network Interface Controller (NIC) are timestamped and reported to the screen display. The current version of ETestTool runs as an MPW tool using MPW 2.0 shell or greater. Due to it's UNIX-like structure, the tool may be easily ported to run under A/UX, if desired. This program only reports the statistics of network activity; there is little interpretation of card "Pass" or "Fail" done by the program. As such, one should be familiar with the NIC documentation in order to interpret many of the subtle problems that may exist on a card. The following errors are timestamped & reported to the Macintosh II screen and can be optionally saved to a disk file: • Card RAM failure • 3Com board rework failure • Slot manager failure • CRC, Frame alignment, FIFO overrun errors • FIFO underrun errors • Missed packets due to buffer overflows • Packets lost without an error status reported on either the transmjtter or receiver NIC / In addition, the following occurrences are tallied: • Total packets sent • Number of packet transmissions lost or corrupted • Average number of retries per packet transmission • Number of packets received with CRC errors and/or frame alignment errors • Number of packets missed due to buffer overflow • Number of FIFO overruns and underruns • Number of excessive collisions, out of window collisions • Number of carrier sense lost & collision detect heatbeat failures • Number of transmission timeouts • Number of multicast packets received (none are currently sent by the program) Startin~ the Verification Test Copy the file named ETestTool into the folder which contains the MPW 2.0 (or greater) Shell application. After double-clicking the MPW shell icon to start that application, select the New menu item from the File menu and name the window as you would like the ETestTool result file to appear. In this new window type the following, being certain to use the enter key at the end: ETestTool The test will automatically search for valid etherTalk cards, and will echo each card's slot number. After checking RAM size and verifying the RAM, the test for the 3Com rework is run. Failures are noted before running the packet transfer test. After the rework test, packets are sent from card to card, and errors are noted as they occur. To get the current error accumulatrion status and to pause, hit the mouse button. Press the mouse button again to continue testing. The cursor will spin a quarter turn for every 125 packets sent. To stop testing, simultaneously press the Command (Apple icon) and the period keys. The results may then be…

TFB SPECIFICATION Frame buffer specification for 1 February 1986. comments and questions are encouraged, direct them to Toby Farrand at MIS 22Y x2524. TFB Specification Apple Confidential UPDATES TO THE SPECIFICATION The following is a list of changes made to the frame buffer specification for the 28 June 1985 version of the document. 123456789- Support for the planar color model has been dropped from section 1.3. The frame buffer memory map has been updated in section 2.0. Many of the control register definitions have changed in section 3.0. Several pin definitions have changed in section 4.0. Test mode operation has changed, and is explained in section 4.3. Planar mode accesses have been eliminated. Data transfer cycles are changed in section 5.2. Appendix A has been added to suggest possible configurations using the TFB. Timing information has been added in Appendix B. The following is a list of changes made to the frame buffer specification for the 1 February 1986 version of the document. These changes apply only to the 1.1 version of the TFB. 12345678911 10 - Support for variable depth color has been added to the chip. Support for multiplexed address and data buses has been added to the chip. The speed of the chip has been increased substantially. The bus interface has been simplified. The chip parameter descriptions have been rewritten and elaborated on. The SCI- pin has been eliminated in favor of a pixel clock output pin. The DS- pin has been eliminated in favor of a dedicated test mode pin. The definitions and timing of the WEN and CMA buses have been changed. All of the figures and diagrams have been updated. Several configuration paramenter have been added. The appendicies have been updated. 1 February 1986 1 Toby Farrand Apple Confidential TFB Specification TABLE OF CONTENTS 1.0 INTRODUCTION 3 1.1 1.2 1.3 3 4 How to Read this Document System Configuration Features 2.0 DATA ORGANIZATION 5 3.0 CONTROL REGISTER DESCRIPTION 5 3.1 3.2 3.3 6 9 3.4 4.0 5.0 System Configuration Parameters Horizontal Timing Parameters Vertical Timing Parameters Initialization Procedure 11 12 SIGNAL DESCRIPTION 12 4.1 4.2 Inputs Outputs 13 15 Bus Operation 17 5.1 5.2 5.3 17 17 18 RAMCycle Data Transfer Cycle Refresh Cycle 6.0 Future Directions 18 6.0 Conclusion 19 Appendix A - Application Note. 20 Appendix B - Electrical Specifications. 24 Appendix C - Pinout and Mechanical Data. 31 1 February 1986 2 Toby Farrand Apple Confidential TFB Specification 1.0 INTRODUCTION One distinguishing characteristic of Apple's computer products is the tight coupling our machines have between their memory and video systems. This tight coupling results in products which have superior graphics in terms of resolution, speed and cost. This architecture's costs are significant,however, as the video refresh circuitry typically consumes between 40-50% of the available bus bandwidth. The demand for increased processor speed, …

United States Patent (19) 11 45 Fitch et al. (54) SELF-CONFIGURING MEMORY MANAGEMENT SYSTEM WITH ON CARD CRCUTRY FOR NON-CONTENTIOUS ALLOCATION OF RESERVED MEMORY SPACE AMONG EXPANSON CARDS (75) Inventors: Jonathan Fitch, Cupertino; Ronald Hochsprung, Saratoga, both of Calif. (73) Assignee: Apple Computer, Inc., Cupertino, Calif. (21) Appl. No.: 25,500 Patent Number: Date of Patent: 4,905,182 Feb. 27, 1990 OTHER PUBLICATIONS Nu Machine Nu Bus Specification; Texas Instruments; Publication No. TI-2242825-0001; 1983. Texas Instruments; Explorer, Publication No. 2537171-0001; Dec., 1985. NuBus-A Simple 32 Bit Backplane Bus P1196 Specifi cation Draft 2.0, (IEEE), Dec. 15th, 1986, This Docu ment is a Draft Specification of the P1196 Working Group of the Microprocessors Standards Committee of IEEE, (pp. 1-60). Primary Examiner-Raulfe B. Zache Assistant Examiner-Malcolm G. Andrews Attorney, Agent, or Firm-Blakely, Sokoloff, Taylor & Zafiman 22) Filed: Mar. 13, 1987 (51) Int. Cl'....................... G06F 13/14; G06F 13/36 (52) U.S. C. ................................. 364/900; 364/935.4; 364/935.44; 364/964.4 (58) Field of Search ........................ 364/200, 900, 421 (56) References Cited U.S. PATENT DOCUMENTS 3,675,083 7/1972. White .................................. 317/101 3,710,324 1/1973 Cohen et al. ......... ... 364/200 3,993,981 1/1976 Cassarino, Jr. et al. ... 364/200 4,000,485 12/1976 Barlow et al. ....... ... 364/200 4,250,563 2/1981 Struger ............. ... 364/900 4,633,402 12/1986 Flinchbaugh ....................... 364/421 FOREIGN PATENT DOCUMENTS 1380776 1/1975 United Kingdom. 2060961 5/1981 United Kingdom . 2101370 1/1983 United Kingdom . 2103397 2/1983 United Kingdom . (57) ABSTRACT A printed circuit board card adapted to fit into a slot and make electrical connections with cooperating ter minals in the slot, the slot being disposed on the main circuit board of a personal computer system, the main circuit board including a CPU, memory, a 32-bit ad dress bus with control signals associated therewith, and input/output circuitry. The slot is coupled to the 32-bit address bus, being substantially a NUBUS bus, and the slot includes distinct identification line means which provide the slot with an identification number (distinct number) in the computer system. The card includes a decoder means which is coupled to the slot to receive the identification number; the decoder means has nem ory reservation means which causes 256 megabytes of memory space to be reserved for the card in the slot, such that, where the slot number is X, the 256 mega bytes of reserved memory space begins at location SX000 0000 and ends at locations SXFFFFFFF. 10 Claims, 7 Drawing Sheets U.S. Patent Feb. 27, 1990 Sheet 1 of 7 4,905,182 5 . ... CPU 3. 3. 7 IAO NTERFACE ( 9 CPU MOTHER BOARD MEMORY 25 U.S. Patent Feb. 27, 1990 Sheet 2 of 7 4,905,182 PHYSICAL ADDRESS MEMORY SPACE $ FFFF SMALL SPACES FFFF SFOOO OOOO $E SUP…

Apple. Macintosh.Coprocessor Platfonn,. Developer's Guide Beta Draft, 29 November 1989 Networking &: Communications Publications Network Integration Group Keith Grigoletto Apple ContldenHal • APPLE COMPUTEll, INC. This manual is copyrighted by Apple, with all rights reserved. Under the copyright laws, this manual may not be ropied, in whole or in part, without the written consent of Apple Computer, Inc. This exception does not allow copies to be made for others, whether or nct sold, but all of the material purchased may be sold, given or lent to another person. Under the law, copying includes translating into another language. (l Apple Computer, Inc., 1987, lses,l~ 20525 Mariani Avenue Cupertino, California 95014 (4re)?)6.1010 Apple, the Apple logo, AppleTaIk, LaserWriter, and Macintosh are registered trademarks of Apple Computer, Inc. AlROSE, Loca1Talk, the Macintosh Coprocessor Platform, and MPW are trademarks of Apple Computer, Inc. ASf and AST-ICP are trademarks of ASr Research, Inc. DEC is a trademark of the Digital Equipment Corporation. Ethernet Is a trademark of 11 NuBus is a trademark of Texas Instruments. Systems Network Architecture (SNA) is a registered trademark of International Business Machines Corpaation. Simultaneously published in the United States and Canada. Contents Figures and tables / xx Preface / xx What you should know How to use this guide Equipment and system requirements Important safety instructions Conventions used in this guide / xx Terminology Part I Getting Started With MCP 1 What Is MOJ? / 1·1 The canponents of MCP / 1-2 The MCP hardware / 1-3 The MCP software / 1-4 AlROSE /1-5 IAlROS! Prep / 1~ Developmental diagnostics / 1~ Developing with MCP / 1-6 Development opportunities and applications / 1-7 Off-loading task processing / 1-8 Parallel processing / 1-8 Interfacing or controlling / 1-8 Data acquisition / 1-8 Intemetworking / 1-8 limitations / 1-9 2 Getting Started / 2-1 Preparing to use MCP / 2-2 Installing the MCP card / 2-2 Installing MCP software / 2-6 Installing the AlROSE Prep driver / 2~ I viii Running a sample program / 2-7 Selecting files for the sample exercise / 2-8 Downloading files to the card / 2-10 Verifying the sample exercise / 2-10 Where do you go from here? / 2-12 iv Contents Part n Software Development / 3 The MCP Software Interface / 3-1 What is A/ROSE? / 3-2 A/ROSE primitives / 3-2 AlROSE utilities / 3-2 AlROSE managers f 3-2 Echo Manager / H InleICard Communications Manager QCCM) / 3-5 Name Mana8er I 3-5 Print Manaser I 3-5 Remote System Manager (RSM) I 3-5 Tuner library and Tuner Manager / 3-6 Trace Manager I 3-6 What is A/ROSE Prep? / 3-7 A/ROSE Prep driver / 3-7 A/ROSE Prep library / 3-8 A/ROSE Prep managers / 3-8 FunC1ions of MCP software / 3-8 Using messages for interprocess communication / 3-9 Message structures I 3-9 Mechanisms for data transfer I 3-13 Message and status codes I 3-14 The dient/server relationship / 3-14 Client and server ruruUns orr …

Macintosh OS Ethernet Driver Design Specification Proposal Alan B. Oppenheimer May 18, 1987 The following is a proposal for a Macintosh Ethernet driver. It is envisioned to be useable for any Ethernet implementation (card, SCSI device, etc.). The interface is such that it should also be applicable to other networks (e.g. Token Ring) with little or no changes. This proposal is for a general-purpose Ethernet driver, and does not address the issue of Apple Talk protocols running on Ethernet hardware. It conforms to IEEE 802.2 Type 1 service. Macintosh network developers are familiar with the Apple Talk driver interface; this interface is patterned directly after that. See the Apple Talk Manager chapter in volume 2 of Inside Macintosh for data structure details. Opening the Ethernet ddyer: The Ethernet driver is opened through a device manager Open call, indicating the slot (for a Mac II) in which the Ethernet card is installed. The driver is initially opened in "Apple Talk" mode. In this mode, packets sent by the driver are restricted to a maximum of 768 bytes. This is big enough to encapsulate AppleTalk packets, and allows more of a shared buffer pool to be allocated for packet reception. The driver can be changed to "general" mode, where it will transmit any valid Ethernet packet, through a control call defined below. The name of the Ethernet driver is '.ENEr. Commands to the Ethernet driver: Commands to the Ethernet driver are specified by means of Device Manager Control calls, with arguments passed in the queue element starting at CSParam. The following is a list of commands: EAttachPH: attach a "protocol handler" to the driver. Arguments are a two-byte protocol type and a handler address. The handler will be called (see "protocol handlers" below) when a packet of its type is received. If the protocol handler address is zero, a "default" protocol handler will be supplied by the driver which will enable the caller to issue standard read calls for that protocol type (see the ERead call). Note: to attach (or detach) a handler for 802.3 (which use protocol types O through $5DC), specify protocol type zero. EDetachPH: detach (remove) the protocol handler for the given protocol type. All pending reads are aborted with an error. EWrite: write out a packet on the Ethernet. The only argument is a WDS (write data structure) pointer. The WDS is a series of length/pointer pairs, terminated by a zero length. The data is "gathered" from each of the WDS entries, in the order provided. The first entry must start with the destination address (6 bytes for Ethernet), and then contain 6 unused bytes (in the Ethernet case) followed by the two-byte protocol type field. Data may then follow if desired. Ethernet Driver - DRAFT Apple Confidential Page 1 If the total length of the packet is too big (greater than 1514 bytes if "general", or 768 bytes if "AppleTalk" mode) an error is returned. If the total length of the packet is too small (less than 60 bytes for Ethe…

Apple Confidential TFB Specification UPDATES TO THE SPECIFICATION The following is a list of changes made to the frame buffer specification for the 28 June 1985 version of the document. 123456789- Support for the planar color model has been dropped from section 1.3. The frame buffer memory map has been updated in section 2.0. Many of the control register definitions have changed in section 3.0. Several pin definitions have changed in section 4.0. Test mode operation has changed, and is explained in section 4.3. Planar mode accesses have been eliminated. Data transfer cycles are changed in section 5.2. Appendix A has been added to suggest possible configurations using the TFB. Timing information has been added in Appendix B. The following is a list of changes made to the frame buffer specification for the 1 February 1986 version of the document. These changes apply only to the 1.1 version of the TFB. 12345678911 10 - Support for variable depth color has been added to the chip. Support for multiplexed address and data buses has been added to the chip. The speed of the chip has been increased substantially. The bus interlace has been simplified. The chip parameter descriptions have been rewritten and elaborated on. The SCl-pin has been eliminated in favor of a pixel clock output pin. The DS- pin has been eliminated in favor of a dedicated test mode pin. The definitions and timing of the WEN and CMA buses have been changed. All of the figures and diagrams have been updated. Several configuration paramenter have been added. The appendicies have been updated. The following is a list of changes made to the frame buffer specification for the 24 October 1986 version of the document. These changes apply only to the 1.2 version of the TFB. 12- Only rowbytes which are powers of two are supported. The CMA bus definition has changed. 7 November 1986 1 Toby Farrand Apple Confidential TFB Specification TABLE OF CONTENTS 1.0 INTRODUCTION 3 1.1 1.2 1.3 3 4 How to Read this Document System Configuration Features 2.0 DATA ORGANIZATION 5 3.0 CONTROL REGISTER DESCRIPTION 5 3.1 3.2 3.3 3.4 4.0 5.0 System Configuration Parameters Horizontal Timing Parameters Vertical Timing Parameters Initialization Procedure 6 9 11 12 SIGNAL DESCRIPTION 12 4.1 4.2 Inputs Outputs 13 15 Bus Operation 17 5.1 5.2 5.3 17 17 18 RAM Cycle Data Transfer Cycle Refresh Cycle 6.0 Future Directions 18 6.0 Conclusion 19 Appendix A - Application Note. 20 Appendix B - Electrical Specifications. 24 Appendix C - Pinout and Mechanical Data. 31 7 November 1986 2 Toby Farrand Apple Confidential TFB Specification 1.0 INTRODUCTION One distinguishing characteristic of Apple's computer products is the tight coupling our machines have between their memory and video systems. This tight coupling results in products which have superior graphics in terms of resolution, speed and cost. This architecture's costs are significant,however, as the video refresh…

MCP BASED DMA SERIAL CARD ("Livonia") REV 1.4.2 (PVT PHASE) Mark Devon Networking and Communications 11/16/89 TABLE OF CONTENTS 1.1 System Overview 2.1 Processor 2.2 ROM 2.3 RAM 2.4 NuBus Interface 2.5 SCC Interface 3.0 Hardware Description Details 3.1 Address Map 3.2 NuBus Address Space 3.3 Timer 3.4 Reset 3.5 Interrupts 3.6 SCC Access 3.7 Serial I/O Signals 3.8 Serial Status Register 3.9 Configuration 3.10 Connector 4.0 DMA chip and registers 4.1 DMA Interface to MCP Local Bus 4.2 Access to DMA Registers by 68000 4.3 MC68450 DMA to 8530 SCC Interface 5.0 Cabling 6.0 Performance 7.0 Mechanical/Environmental 1.1.2 System Overview The "Livonia" board is a card with a full NuBus Master/Slave interface with a 68000 processor , 1/2 Mbyte of RAM (expandable to 2.5Mb), two SCC's and one Mc68450 DMA chip (4 channels) on board. It is based on Gary Martens' MCP Nubus interface card. The card provides four active ports, two of which can be run at speeds greater than 19.2kbit/s. These two high speed serial ports may be configured as V.35 ports for driving 56kb/s leased line DDS (modem-like) devices, or as RS-232 ports. The configuration choice is made by the type of connecting cable used. The 68000 can access any device on the NuBus. The DMA, EPROM, SCC's, local RAM and DTR/DSR registers and all may be accessed via Nubus. Accesses by the DMA to the Nubus are NOT supported. 2.1 Processor The I/O Processor utilizes a 10MHz 68000 processor with no wait states for accesses to onboard RAM. The 10MHz clock is derived from the 10MHz NuBus clock. All access by the 68000 are implemented by a 16-bit data bus with byte mode also supported. Accesses to the SCCs are done on a byte wide basis on D0-7 (odd addresses). Accesses to the DMA may be either byte or word mode. 2.2 ROM The 16-bit wide ROM is implemented with two 256K bit ROMS yielding a 64K byte ROM space. The ROM serves as "power-up" code for the 68000, a place for user firmware, and it also stores the NuBus ID data for the card. The ROM inserts one wait state when accessed by the onboard 68000. To the NuBus interface, ROM appears as a full 32-bit wide device, supporting 8-bit, 16-bit and 32-bit bus reads. 2.3 RAM The card contains 1/2 Mbyte of 16-bit wide dynamic RAM, with sockets available for a second 1/2 Mbyte (all ZIP chips). RAM is accessed by the 68000, NuBus, and the two DMA Chips (MC68450). When any device on the card is accessed via NuBus, the 68000 is locked out from all accesses. RAM starts at location 000000, with the default 1/2 Mbyte of RAM, the last RAM address is 07FFFF. When the 68000 accesses onboard RAM, no wait states are inserted. When the 68450 DMA chip accesses RAM, one wait state is inserted on write cycles, zero wait states inserted on read cycles (this is an anomaly in the DMA chip itself). Provision is made for future 4 Mbit DRAM ZIP chips (Qty. 4) which, when combined with the 1/2 Mbyte already present would give total of 2.5 Mbyte of RAM on the card. Pin 10 of the 1Mb …