Apple Confidential TFB Specification UPDATES TO THE SPECIFICATION The following is a list of changes made to the frame buffer specification for the 28 June 1985 version of the document. 123456789- Support for the planar color model has been dropped from section 1.3. The frame buffer memory map has been updated in section 2.0. Many of the control register definitions have changed in section 3.0. Several pin definitions have changed in section 4.0. Test mode operation has changed, and is explained in section 4.3. Planar mode accesses have been eliminated. Data transfer cycles are changed in section 5.2. Appendix A has been added to suggest possible configurations using the TFB. Timing information has been added in Appendix B. The following is a list of changes made to the frame buffer specification for the 1 February 1986 version of the document. These changes apply only to the 1.1 version of the TFB. 12345678911 10 - Support for variable depth color has been added to the chip. Support for multiplexed address and data buses has been added to the chip. The speed of the chip has been increased substantially. The bus interlace has been simplified. The chip parameter descriptions have been rewritten and elaborated on. The SCl-pin has been eliminated in favor of a pixel clock output pin. The DS- pin has been eliminated in favor of a dedicated test mode pin. The definitions and timing of the WEN and CMA buses have been changed. All of the figures and diagrams have been updated. Several configuration paramenter have been added. The appendicies have been updated. The following is a list of changes made to the frame buffer specification for the 24 October 1986 version of the document. These changes apply only to the 1.2 version of the TFB. 12- Only rowbytes which are powers of two are supported. The CMA bus definition has changed. 7 November 1986 1 Toby Farrand Apple Confidential TFB Specification TABLE OF CONTENTS 1.0 INTRODUCTION 3 1.1 1.2 1.3 3 4 How to Read this Document System Configuration Features 2.0 DATA ORGANIZATION 5 3.0 CONTROL REGISTER DESCRIPTION 5 3.1 3.2 3.3 3.4 4.0 5.0 System Configuration Parameters Horizontal Timing Parameters Vertical Timing Parameters Initialization Procedure 6 9 11 12 SIGNAL DESCRIPTION 12 4.1 4.2 Inputs Outputs 13 15 Bus Operation 17 5.1 5.2 5.3 17 17 18 RAM Cycle Data Transfer Cycle Refresh Cycle 6.0 Future Directions 18 6.0 Conclusion 19 Appendix A - Application Note. 20 Appendix B - Electrical Specifications. 24 Appendix C - Pinout and Mechanical Data. 31 7 November 1986 2 Toby Farrand Apple Confidential TFB Specification 1.0 INTRODUCTION One distinguishing characteristic of Apple's computer products is the tight coupling our machines have between their memory and video systems. This tight coupling results in products which have superior graphics in terms of resolution, speed and cost. This architecture's costs are significant,however, as the video refresh…

NuBus Graphics Card Theory of Operations Toby Farrand Advanced Development Group Computer Graphics Lab 12 August 1986 - ! , NuBus Graphics Card Theory of Operations Toby Farrand Updates to the Specification • This specification applies only to the DVT version of the NGC labeled 1.0. • The CLUT register spaces have moved. • No reads of the card's control of status bits are supported. • The configuration ROM is now lK bytes. • A section on debugging of the card has been added. 12August1986 1 Apple Confidential NuBus Graphics Card Theory of Operations Toby Farrand Table of Contents 1.0 2.0 Overview 3 1.1 Features 1.2 -Cost 3 3 Software Interface 4 2.1 Memory Map 2.2 TFB Operation 4 5 2.2.1 TFB Register Values 2.2.2 TFB Initialization 3.0 5 7 Hardware Description 3.1 3.2 3.3 3.4 7 NuBus Interface Timing Generation Frame Buffer Video Output 8 8 8 9 4.0 Schedule 9 5.0 Debugging 9 6.0 Final Board Features 11 7.0 Layout 12 8.0 Schematics 15 9.0 PAL Equations 24 10.0 Timings 27 11.0 Bt453 Specification 29 12 August 1986 2 Apple Confidential NuBus Graphics Card Theory of Operations 1.0 Toby Farrand Overview The NuBus Graphics Card (NGC) is a high performance, flexible and low cost color graphics card for any Apple NuBus based product The card is based on the TFB frame buffer controller chip designed in the Advanced Development Group, and is targeted for introduction with the Milwaukee machine. 1.1 Features The NOC features variable color depth operation of either 1,2,4 or 8 bits per pixel with a color lookup table providing a palette of 16M colors driving 8 bit DACs for each of the ROB channels. The card is capable of generating proper timing for the Milwaukee monitors, or any RS 170 compatible monitor. (This includes such things as analog film recorders and projection TVs.) The board features high performance -- 400ns reads and writes from the NuBus interface. 1.2 Cost The board is expected to cost no more than $110 for the 512K byte version capable of supporting up to 8 bits per pixel color. A cost breakdown is given below: ITEM APPLE PART PART DESCRIPTION NUMBER ---- -------- QUANTITY PER BOARD EST. UNIT COST PART COST PER BOARD ---------------------- ---------- ---------- ----------- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 TFB (Apple Custom) NEC video RAM µPD41264150ns PAL16R4B 15ns PAL PAL 20R6A 25ns PAL Brooktree Bt453 CLUT/DAC Chip 2716 16K EPROM 74F153 Dual 4:1 MUX AM29841 Ten Bit Latch 74F521 Octal Comparator 74F245 Octal Buffer 74FOO QUAD NANO Gate 74F38 QUAD NANO Gate HY5030-100 Tapped Delay Line 12.2727 MHz Oscillator 30.2400 MHz Oscillator 96 Pin NuBus Connector D-Shell 15 pin connector LM385-1.2 Voltage Reference .1 µF Decoupling Capacitor 10µF Bulk Capacitor Ferrite Bead Resistor SIP Pack 10 pin 22 ohm Resistor, 3.3K ohm 5% Resistor, 47K ohm 5% Resistor, 75 ohm 5% PC Board, 4 layer 4" X 13" 1 16 1 1 1 1 1 1 1 14.50 3.00 1.75 1.7…

r REV. ZONE ECO# APPD REVISION A R1416 PRODUCTION RELEASE A R2162 RECORD CHANGE DATE MT 8-9-90 NOTE: MANUFACTURERS RECEIVING APPLE APPROVED VENDOR STATUS FOR THEIR PRODUCT UNDER THIS PART NUMBER PLEASE NOTE: You mJst not change your part design, materials or manufacturing process from those used for the original samples submitted to and approved by Apple without written approval of Apple. Proposed changes determined by Apple to be significant, will require the manufacturer to submit new samples and/or data for review and approval prior to product shipments to Apple. r -$-E3DIMENSIONS ARE IN MIWMETERS. DIMENSIONS IN BRACKETS [ ) ARE IN INCHF.S. TOLERANCES X.X± ., ... 0.3 [.01] 0.13 [.005] x.xxx ± 0.03 [.001] ;; ANGLEs ± 0.1 or as noted \.. DRAYf M.T. ENG APl'D D.I. /$/ 88 :Xv 88 QA APl'D X.XX± DO NOT SCALE ORAWING .® METRIC // RELEASE D.B. DESIGN CK S.R. MFG APl'D A.A. DESIGNER /a/,,88 .Av 89 // SCALE /'3L 89 MATERIAL/FINISH N01ED AS APPLICABLE NONE SIZE A Apple Computer, Inc. NOTI<ll OP PROPRIETARY PROPl3RTY THE INFORMATION CONrAINED HEREIN IS THE PROPRIETARY PROPllRTY OP APl'Ul CDMPU'JllR, INC. THE POSSESSOR AGREES TO 1lIB FOILOWING: (i) TO MAINTAIN TIIIS DOCUMENT IN CDNFIDENCE (ii) Naf TO REPRODUCE OR COPY IT (iii) Naf TO REVEAL OR PUBLISH IT IN WHOLE OR PART TITLE IC, CUSTOM, TFB2.2 144-QFP DRAWING NUMBER 34380077-A SHT 1~0 ..) 1.0 SCOPE: This specifies the parametric requirements of TFB2.2. The TFB2.2 is designed to interface with NuBus, to sense what monitor is used, and generate the corresponding monitor timing, video RAM timing, control and video data for Color look-up table. It is packaged in a 144 pin plastic square quad flat pack. The TFB2.2 is designed to replace Apple P/N 34350019 (TFB2.0) The main difference between TFB2.2 and TFB2.0 are as follow: 1. TFB2.2 extend the enable outputs of ADS, AD9, AD10, AD11 (pin 49, 50, 51, and 52) by 25 ns. 2. TFB2.2 support the NuBus Block Move Access, it effects /ACK, /TM1, and /TMO (pin 43, 53, and 45). 3. TFB2.2 support 1bit/pxl and 2bit/pxl modes, it presents the correct data on the CA Bus (pin 118-125, 128-135). Note: A copy of TFB2.2 schematic is on file in Documentation for Apple Internal use only. Do not remove the original schematic 062-0071 from Documentation files. VD20 VD2 VD1 VD21 VD22 VDO /TSlE VD23 VD24 VD25 SENSE2 SENSE1 SENSEO VD26 VD27 VD28 VD29 VD30 VD31 PXIN GNO /CBLK /CSYN NSYN /SOEO IHSYN /SOE1 A13 A12 A11 IDOEO IDOE1 sco PXOUT GND VDD GNO VDD /RA.SO A10 /RAS1 IC/ISO /CAS1 GND RAO /JS AB A7 N; A5 A4 A'3 RA1 RA2 RA3 GND /SLOT AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 VDD RA4 RA5 RAB RA7 GND N/ENO FIGURE 1. PIN CONFIGURATION \ #._ SIZE DRAWING •®Apple Computer, lnc..,_____......3_4_3s_o_o1_1_-A_ ______ SCALE SHT 2 OP 30 r 1.1 PIN DESCRIPTION INPUTS PIN NAME PIN# DESCRIPTION /10MO /10M1 /RESET AD(7:0) AD(19:12) /SLOTS EL PXIN SENSE(2:0) VD(31 :0) 46 47 48 72-65 80-73 81 101 1…

TFB SPECIFICATION Frame buffer specification for 1 February 1986. comments and questions are encouraged, direct them to Toby Farrand at MIS 22Y x2524. TFB Specification Apple Confidential UPDATES TO THE SPECIFICATION The following is a list of changes made to the frame buffer specification for the 28 June 1985 version of the document. 123456789- Support for the planar color model has been dropped from section 1.3. The frame buffer memory map has been updated in section 2.0. Many of the control register definitions have changed in section 3.0. Several pin definitions have changed in section 4.0. Test mode operation has changed, and is explained in section 4.3. Planar mode accesses have been eliminated. Data transfer cycles are changed in section 5.2. Appendix A has been added to suggest possible configurations using the TFB. Timing information has been added in Appendix B. The following is a list of changes made to the frame buffer specification for the 1 February 1986 version of the document. These changes apply only to the 1.1 version of the TFB. 12345678911 10 - Support for variable depth color has been added to the chip. Support for multiplexed address and data buses has been added to the chip. The speed of the chip has been increased substantially. The bus interface has been simplified. The chip parameter descriptions have been rewritten and elaborated on. The SCI- pin has been eliminated in favor of a pixel clock output pin. The DS- pin has been eliminated in favor of a dedicated test mode pin. The definitions and timing of the WEN and CMA buses have been changed. All of the figures and diagrams have been updated. Several configuration paramenter have been added. The appendicies have been updated. 1 February 1986 1 Toby Farrand Apple Confidential TFB Specification TABLE OF CONTENTS 1.0 INTRODUCTION 3 1.1 1.2 1.3 3 4 How to Read this Document System Configuration Features 2.0 DATA ORGANIZATION 5 3.0 CONTROL REGISTER DESCRIPTION 5 3.1 3.2 3.3 6 9 3.4 4.0 5.0 System Configuration Parameters Horizontal Timing Parameters Vertical Timing Parameters Initialization Procedure 11 12 SIGNAL DESCRIPTION 12 4.1 4.2 Inputs Outputs 13 15 Bus Operation 17 5.1 5.2 5.3 17 17 18 RAMCycle Data Transfer Cycle Refresh Cycle 6.0 Future Directions 18 6.0 Conclusion 19 Appendix A - Application Note. 20 Appendix B - Electrical Specifications. 24 Appendix C - Pinout and Mechanical Data. 31 1 February 1986 2 Toby Farrand Apple Confidential TFB Specification 1.0 INTRODUCTION One distinguishing characteristic of Apple's computer products is the tight coupling our machines have between their memory and video systems. This tight coupling results in products which have superior graphics in terms of resolution, speed and cost. This architecture's costs are significant,however, as the video refresh circuitry typically consumes between 40-50% of the available bus bandwidth. The demand for increased processor speed, …