RasterOps 8XL/GSXL Specification Revision A1 February 19, 1990 Jeff Tingley RasterOps Corporation PART # 0002-0228 RasterOps BXUGSXL Specification February 19, 1991 1.0 Introduction This document establishes the physical and electrical characteristics for the RasterOps 8XlJGSXL Graphics Display System. The RasterOps 8XlJGSXL, referred to as 8XL throughout the rest of this document, is a very high resolution, very high speed, graphics display system for the Macintosh II family of computers. The 8XL occupies 1 Nubus slot. It is capable of five pixel depths and several resolutions. A block diagram of the 8XL is shown in Figure 1-1. This document is the property of RasterOps Corporation and is confidential. Reproduction of this document is prohibited. RGS14188 VRAM Contrd Local Config. EEROM HghSpeedNulluo _ _ _ _Addtess _ _Bui ___................., . . _ _ Colorlloard ,......_ ....i Accolellllor Cdorl!oard Dala Bua Dil!My Memooy CdorBoerd Data Bua 1024x1024. 8 (1 Mertel Figure 1-1 8XL Block Diagram 2.0 Hardware Description 2.1 Features Switchable Resolutions of (Software Selectable) - 1152 x 870 (72 Hz Vertical Refresh) - 1024 x 768 (75 Hz Vertical Refresh) - 1024 x 768 (60 Hz Vertical Refresh) -800 x 600 -640 x 870 - 640 x 480 (66 Hz Non-interlaced) 2 BT478-110 February 19, 1991 RasterOps BXUGSXL Specification - 640 x 480 (30 Hz Interlaced) Pixel Depths of 1, 2, 4, and 8-bits Macintosh II "FAT" and "Skinny" NuBus Compatible ·1s.7 Million Color Palette 100, 80, 64, 57, 50, and 30.24, 12.2727 MHz Video Rate Single NuBus Slot Current Consumption of 1.5 Amps at 5 Volts Full Block Mode Support In All Bit-depths RS-343 Compatible 15-Pin D-Submininature Connector (Same as Apple) Hardware Zoom of 1x, 2x, 4x, and Bx Hardware Pan Extended Desktop State of the Art Surface Mount Technology Including three ASICs Supports the RasterOps Accelerator 2.2 Overview The 8XL is a stand alone frame buffer. This means one can plug this card into a NuBus Slot on a Macintosh and display up to 8-bits per pixel in one of several resolutions. As an added feature the 8XL also supports a direct interface, through the NuBus, to the RasterOps Accelerator. This card provides QuickDraw acceleration capabilities making the 8XL much faster when manipulating images in any bitdepth. 3 RasterOps BXUGSXL Specification February 19, 1991 3.0 Technical Data 3.1. Absolute Maximum Ratings Supply Voltage, VCC ......................................•............... Operating Ambient Temperature Range ......•..........•.... Storage Temperature ...................................................... ICC (Supply Current) .................................•..........•.... 5.25 Volts 0°Cto60°C -65 °C to 150 °C 1.5A@5.25 V 3.2 Reference Drawings The following items should be referenced for information on the 8XL. 8XL Top Assembly LM 8XL Assembly Drawing 8XL Schematics 8XL PCB Fab 8XL LJM 8XL Manual 8XL 0002-0224 0002-0223 0002-0225 0002-0226 0700-0069 3.3 Video Specifica…

Accelerator board Model 800 Specification Revision 02 September 12, 1990 Dave Smith 1ssurn )\t J. !; 1 \j RasterOps Corporation oocuMENT PART# 0002-0154 ORIGINAL Introduction The Accelerator is a dedicated longword BITBLT-FILL engine optimized for the NuBus. The Accelerator has 8 modes of operation: FILL-CONSTANT, FILL-PA1TERN, PRAM-FILL, BITBLT, INVERT-FILL, INVERT-PA1TERN, INVERT-PRAM-FILL, and INVERT-BITBLT. In addition the programmer can enable BUS-LOCKING to prevent other NuBus masters from interrupting an operation.This function combined with automatic Block Transfer enable the Accelerator to fill data at a peak rate of 9 million pixels-per-second, and blit data at a peak rate of 4.5 million pixels-per second on a fast block mode video board. The Accelerator has been designed for maximum performance by minimizing the amount of software overhead required to initiate an operation and by a novel use of a large pixel Cache (SRAM). A flexible architecture has been created which allows any 32 bit address within the Macintosh computer to be accessed for each operation. A programmable translation memory (TRAM) is placed discontinuous data the motherboard to the video board. This function is required for the Macintosh Ilci and future machines with non-contiguous main memory. A large pixmap memory (PRAM) is included to allow offscreen pixmaps to reside locally and to be moved at high speed to the video cards. The Accelerator can support up to two Block-Mode capable videocards and an unlimited number of non-Block-Mode video cards. The Accelerator is not limited to just video cards, but can be used with memory cards as well. The Accelerator resides in its own NuBus slot and has a power consumption of 2 Amp. Reference Documents The following is a list of related documents for the Accelerator product: Schematic ,. 0002-0149 Assembly Drawing 0002-0150 PC Fab drawing/Artwork 0002-0151 Board List of Materials 0002-0152 Top Assembly LM 800 Manual 0700-0044 Block Diagram -AD(31 :0) TRANSLATION RAM I---' ADDRESSGENEPATOR CHIP N u .____ ADDRESS c 20-26 I---' 1-- B u s 1 I N T PIXMAP MEMORY 1---J 4-16 MEGS T 1-- E R F A c E ,. DATAGENERATCFl CHIP BK BYTE PIXEL CACHE ADD i--- DATA Accelerator Register Address Map FSFF Fxxx ID REGISTER FSFF C020 PRAM POINTER FSFFC01C MODE REGISTER FSFF C018 BLOCK COMPARE #2 FSFF C014 BLOCK COMPARE #1 FSFF C010 COUNT LENGTH FSFFCOOC SRAM POINTER FSFF COOS SEMAPHORE POINTER FSFF C004 DESTINATION POINTER FSFF COOO SOURCE POINTER FSFFA3FC TRANSLATION TRAM 1K BYTES FSFFAOOO FSFF9FFC PIXEL CACHE SRAM BK BYTES FSFF 8000 Pixel Cache SRAM The Pixel Cache SRAM (SRAM will be used from now on) is comprised of four 2048 x 8-25ns static rams arranged as long words. The SRAM may be written to or read from whenever the Accelerator is not busy with an operation (FILL, etc.). Locations 0- 1983 are used for BITBLT and Fll.L-CONSTANT mode, while locations 1984 - 2047 ar…

ColorBoard 264 (Cheapskate) Specification July 28, 1988 Primary Design Goal Replacement for ColorBoard 64 and 64N, with features to support Apple's Full Color QuickDraw, and optional NTSC output via a daughterboard. Once 264 production starts, 64 and 64N production stops. Target Retail Price $1595 Availability Introduction Shipping November 1988 January 1989 Resolution 640x480 640x486 66Hz 30Hz 13" monitor NfSC 72DPI One local oscillator with one external (NTSC). Resolutions are software selectable (no DIP switches), via keyboard at boot time. 1.5 Meg video RAM (1024 x 512 x 24 bits) Pixel Depth 1,2,4,8 and 24 bits per pixel. 1,2,4, and 8 bits per pixel is indexed; 24 bits per pixel is full chunky direct. 24-bit chunky planar hardware available; availability in software with release 1.0 TBD. Chunky planar available in hardware, availability with release 1.0 ROM TBD. Max 256 colors (indexed) and 16.7 million colors (direct) from 16.7 million palette. Configuration ROM 27256 EPROM (32K bytes) Video • RS-343A compatible • 15 pin D-subminiture connectors (same as Apple's) • 35Khz monitors supported (optional 31.49Khz) • VLSI controller • NTSC output (optional) • Separate sync for VGA compatability Slot • Single NuBus slot • 32-bit addressing (fat slot) • X Amps at 5 Volts • NTSC option control bus Register Add 15.0 Bits Default Value CM ODE CM ODE 6004 6008 3RW 3C OSC30HZ NMRQ NMRQ DACCTL 600C 6010 6014 6018 2RW 1RW 1C 2RW FORCEBLK* EXSYNMODE FATSLOT 601C 6020 6024 1RW 1RW 1RW RDOUTST SYNC EN TRANS EN STVTOTAL VCNTRES NM RODIS VSYNEND VBLKGO VTOTAL HSYNCEND HBLKEND HBLKGO HTOTAL HHLFLIN VBLKEND BLKENABLE 6028 602C 6030 6034 6038 603C 6040 6044 6048 604C 6050 6054 6058 605C 6060 6064 1R 1RW 1RW 1R 1RW 1RW 4RW 10RW 10RW 9RW 9RW 9RW 9RW 9RW 6RW 1RW 1** CHUNKY MODE CHUNKY, MODE1 , MODEO 000 1 BIT MODE CHUNKY,MODE1,MODEO 001 2 BIT MODE 010 4 BIT MODE 011 8 BIT MODE OSCSEL , 30 HZ MODE 00 NMRQBIT 0 N/A NMRQBIT OOCHUNKY DACS1,DACSO 10 PSEUDO COLOR 1 FORCE BLANK (ACTIVE LOW) 0 ENABLES EXTERNAL SYNCS 1 FAT SLOT FORCES FAT SLOT ADD DECODE 0 SKINNY SLOT N/A READS MPRES,MTYPE,OPTON 1 ALLOWS SYNC TO GO ACTIVE 1 TRANSFER CYCLE ENABLE N/A READS VTOTAL FROM VIDEO RESETS ALL VIDEO COUNTERS 0 0 DISABLE THE NMRQ INTERUPT 002 HEX VERTICAL SYNC END COUNT 209 HEX VERTICAL BLANK START COUNT 20C HEX VERTICAL TOTAL COUNT OOF HEX HORIZONTAL SYNC END COUNT 027 HEX HORIZONTAL BLANK END COUNT OC7 HEX HORIZONTAL BLANK START COUNT OD7 HEX HORIZONTAL TOTAL COUNT 06B HEX HORIZONTAL HALFLINE COUNT 029 HEX VERTICAL BLANK END COUNT THIS BIT ENABLES BLOCK MODE 0 Bits Definition A-Readable W - writeable C - Clearable Clearing a register is done by writing to the registers clear address with a 1 in each bit position to be cleared. *DONOTCARE Description CHEAPSKATE BOARD ADDRESS SPACE (FAT SLOT) COMPONENTS ADDDRESS SPACE NEEDED IN HEX 20 0000 2M BYTES 0 1000 4K BYTES 0 1000 4K BYTES 0 8000 32K BYTES RAM STATUS DACCONTROL FOv1 ROM ADDRESS LINES ARE AD<14 …

IMAGER BOARD Model800 RasterOps Corporation 0002-0154 March 23, 1990 Revision Bl Introduction The Imager is a dedicated longword BITBLT-Fll.L engine optimized for the NuBus. The Imager has 8 modes of operation: Fll.L-CONSTANT, Fll.L-PATIERN, PRAM-FILL, BITBLT, INVERT-FILL, INVERT-PATTERN, INVERT-PRAM-FILL, and INVERT-BITBLT. In addition the programmer can enable BUS-LOCKING to prevent other NuBus masters from interrupting an operation.This function combined with automatic Block Transfer enable the Imager to fill data at a peak rate of 9 million pixels-per-second, and blit data at a peak rate of 4.5 million pixels-per second on a fast block mode video board The Imager has been designed for maximum performance by minimizing the amount of software overhead required to initiate an operation and by a novel use of a large pixel Cache (SRAM). A flexible architecture has been created which allows any 32 bit address within the Macintosh computer to be accessed for each operation. A programmable translation memory (TRAM) is placed discontinuous data the motherboard to the video board. This function is required for the Macintosh Ilci and future machines with non-contiguous main memory. A large pixmap memory (PRAM) is included to allow offscreen pixmaps to reside locally and to be moved at high speed to the video cards. The Imager can support up to two Block-Mode capable videocards and an unlimited number of non-Block-Mode video cards. The Imager is not limited to just video cards, but can be used with memory cards as well. The Imager resides in its own NuBus slot and has a power consumption of 2 Amp. Reference Documents The following is a list of related documents for the Imager product: Schematic 0002-0149 Assembly Drawing 0002-0150 PC Fab drawing/Artwork 0002-0151 Board List of Materials 0002-0152 Top Assembly LM 800 Manual 0700-0044 Block Diagram -AD(31:0) N u ADDRESS GENERATOR CHIP B e.,-1('·,/1 :·· '" ~- u ', 1 s PIXMAP MEMORY I N T E 4-16 MEGS R F A c E PfdF1r~c DATA GENERATOR CHIP BK BYTE PIXB..CACHE 5 RA ftA, ADD .___ DATA L/ . ;~ j( '/ \ 4,o"·lle, ,.., /lr..-1 -.1rur. . 1. fr. ·. ,)( L iy.'.J < BUSCONTRa...SEQUENCERS Imager Register Address Map ' ~ /t I ID REGISTER FSFF Fxxx ·., (j{)C10 C;oO / ,,.--....._ ,,.--....._ ,,. FSFF C020 k>/_!,J ,,.x.' FSFFC01C w/ /J if '·{ FSFF C018 t /\- "l.Y ?,F r:ff'('. 4- r.\-: ·: PRAM POINTER~. ,, ~r ; 11 , c 1 r ··; BLOCK COMPARE #2 Fct· ,FE er f(t.' r'. .· .. J FSFF C014 FSFF C010 ;J FSFFCOOC I· p FSFF COOS COLJNTLENGTH • ·i FFir''' .~·:·-i.-:1 1/ 5 7. FSFF C004 tu(o r FSFF COOO /) 3 ·1. SEMAPHORE POINTER PIXEL CACHE SRAM 8K BYTES f./-f .~~ ' ·f>'l\ !! / 1 ·./: , ' ' SOURCE POINTER 5ii: ' ' FSFF AOOO FSFF9FFC f /,•"'' .. · ·' cJ /DD'{)r.>Od DESTINATION POINTER ~,~,;' ?: , ·r TRANSLATION TRAM 1K BYTES r- :/- SAAM POINTER FSFFA3FC FSFF 8000 ,,~r. ~-ft', , 1, , , .1: ,' Pixel Cache SRAM The Pixel Cache SRAM (…

Colorboard 264/SE30 Specification Revision A1 June 1, 1989 Brad Patton RasterOps Corporation PART# XXXX-XXXX CB 264/SE30 Specification June 5, 1989 1.0 Introduction This document establishes the physical and electrical characteristics for the Colorboard 264/SE30 system. The Colorboard 264/SE30 is a high resolution, high speed, graphics display card for the Macintosh SE/30. The Colorboard 264/SE30 occupies the '030 direct slot within the SE/30. It is capable of four pixel depths and two resolutions in it's standard configuration. With the addition of a video memory expansion option the number of pixel depths becomes five. A block diagram of the Colorboard 264/SE30 is shown in Figure 1-1. This document is the property of RasterOps Corporation and is confidential. Reproduction of this document is prohibited. ADDRESS DECOD • CONTROL LOGIC ...0 VIDEO CLOCK SOURCE 30.24 MHz NI ....cc c 0 II) II) w a: c c c C'I 0 Ill (0 0 C'I 0 Ill (0 iii TMS34061 N' 01 u II. ui c ui c .100" x .100" HHcllr ~ ffi ~ ..I 0 RAM ARRAY ....z 512 x 512 x 16/48 a: VIDEO BACK END ASIC 8/24 0 u 0 C'I 0 Ill (0 264/30 Block Diagram Figure 1-1 Colorboard 264/SE30 Block Diagram 2 81473 DAC June 5, 1989 CB 264/SE30 Specification 2.0 Hardware Description 2.1 Overview The Colorboard 264/30's function is to provide the Macintosh SE/30 user with a low cost, versatile, high resolution frame buffer. The Colorboard 264/SE30 supports pixel depths of 1, 2, 4 and 8-bit in it's standard configuration with 24-bit becoming available with the addition of the video memory expansion option. Added features include RasterOps Virtual Screen, hardware zooming of 1X, 2X and 4X and hardware panning for full memory utilization and fast image enlargement. 2.2 Features Switchable Standard Resolutions of - 640 x 480 -ZZZxYYY 64K or 256K ROM Available Pixel Depths of 1, 2, 4, 8 and 24-bit {optional) Occupies SE/30's '030 Direct Slot 256 Colors Displayable from a 16.7 Million Color Palette {standard) 16.7 Million Colors Displayable {with option) 35 and 48KHz Monitors Supported Standard Current Consumption of 1.5 Amps at 5 Volts RS-343A Compatible 15-Pin D-Submininature Connector {Same as Apple) Hardware Zoom of 1X, 2X, and 4X Hardware Pan Virtual Desktop 3 CB 264/SE30 Specification June 5, 1989 FCC Class B Certified Utilizes RasterOps "Video Back End" ASIC Separate H and V Sync Signals on the Video Connector for VGA Com patabi lity 3.0 Technical Data 3.1. Absolute Maximum Ratings Supply Voltage, VCC ...............................................................5.25 Volts Operating Ambient Temperature Range .............................. O °C to 60 °C Storage Temperature ............................................................. -65 °C to 150 °C ICC (Supply Current) ...............................................................1.5 A @ 5.0 V 3.2 Reference Drawings The following items should be referenced for detailed information on the Colorboard 264/SE3…

“ Printed By: Jim Huffman 4/12/93 10:49 AM Page: 1 From: David Fung (4/12/93) To: Frank Drobot, Dan Ho, Jim Huffman, Eric Kuo Subject: Time:10:24 AM OFFICE MEMO New Board IDs Date:4/12/93 Jim, Eric, Dan, Frank - Here are the new set of board/drHw IDs assigned by Apple for new products. | gave them non-descriptive names to shield what we were working on: 8Li - (RasterOps A/8) The board ID is $05C5. The functional sResource types are: CatDisplay EQU $0003 TypVideo EQU $0001 DrSwApple EQU $0001 DrHwRasterOpsA/8 EQU $041D Mercury24 (RasterOps A/24) The board ID is $05C4. The functional sResource types are: CatDisplay EQU $0003 TypVideo EQU $0001 DrSwApple EQU $0001 DrHwRasterOpsA/24 EQU $041C | also had three sets defined for the DuoMates: Ren (RasterOps Duo 1): The board ID is $05C1. The functional sResource types are: CatDisplay EQU $0003 TypVideo EQU $0001 DrSwApple EQU $0001 DrHwRasterOpsDuo1 EQU $0419 CatDock EQU $0020 TypStation EQU $0001 DrSwRasterOps EQU $0101 DrHwRasterOpsDuo EQU $0100 Stimpy (RasterOps Duo 2): The board ID is $05C2. The functional sResource types are: CatDisplay EQU $0003 TypVideo EQU $0001 DrSwApple EQU $0001 DrHwRasterOpsDuo2 EQU $041A CatDock EQU $0020 TypStation EQU $0001 DrSwRasterOps EQU $0101 DrHwRasterOpsDuo EQU $0100 Daffy (RasterOps Duo 3): The board ID is $05C3. The functional sResource types are: Printed By: Jim Huffman 4/12/93 10:49 AM Page: 2 CatDisplay EQU $0003 TypVideo EQU $0001 DrSwApple EQU $0001 DrHwRasterOpsDuo3 EQU $041B CatDock EQU $0020 TypStation EQU $0001 DrSwRasterOps EQU $0101 DrHwRasterOpsDuo EQU $0100 | may combine Ren and Stimpy into the same drHwID... Please stop by if you have questions, David Fung, x388

RasterOps RGS14188 User's Guide Preliminary REVISION XA 1 11/2/90 JEFF TINGLEY CONFIDENTIAL THIS DOCUMENT IS THE PROPERTY OF RasterOps REPRODUCllON OF THIS · DOCUMENT IS PROHIBITED . November 2, 1990 RGS14188 User's Guide 1.0 Introduction The RGS14188 Frame Buffer Controller (FBC) is a high-performance CMOS device that controls the video display and dynamic memory of a bit-mapped graphics system. Although the RGS14188 was designed to provide control of varying size, multi-port DRAMs (VRAMs) it works equally well with standard DRAMS and is easily interfaced to a variety of CPUs and buses. The principal role of an FBC is to provide an external processor with virtually unlimited access to (video) memory. It eliminates the delays and overhead caused by display update address generation, reloading shift registers, and DRAM refresh. Furthermore, the FBC reduces the amount of hardware needed to interface a RAM array and provides the user with the utmost flexibility. Highly programmable, the RGS14188 supports a broad range of raster-scan display systems with various resolutions and scan rates. Some of the major functions for RGS14188 FBC are: Generates all control signals necessary to control 256K, 1, 2, and 4 Megabyte VRAM devices, as well as those necessary to control conventional DRAMs of the same sizes. Generates the video synchronization and blanking signals necessary to control a CRT monitor. Accommodates processor data paths of arbitrary widths, working equally well with 8-bit to n-bit processors or bus architectures. Supports both interlaced and non-interlaced displays of essentially any display resolution. Automatically generates the special display-update cycles required by VRAM memories to maintain the CRT display. Automatically performs periodic RAM refresh cycles necessary to maintain the data stored. The block Diagram of a typical system using the RGS14188 is shown in Figure 1-1. 2 RGS14188 User's Guide November 2, 1990 CRT Control Signals RasterOps BGS14188 Host Bus Address Bus DRAM VRAM ROM Video Back End DAC Red Green Blue Data Bus Pixel Clock Figure 1-1 Typical System Using the RGS14188 2.0 Pinout and Signal Descriptions A functional drawing of the RGS14188 is given in Figure 2-1 and the pin number assignments are given in Figure 2-2. A description of each signal is given in the following section. The RGS14188 comes in a 120-terminal plastic quad flat package (PQFP). 3 November 2, 1990 RGS14188 User's Guide Address Input:; ( iP (pull down on (J.7..23] Multiplexed Row and Column Addr CASSelects -RAS1 -RAS2 -RAS3 CASStrobes -CASO -CAS1 -CAS2 -CAS3 Column-address Strobe Column-address Strobe Input latch Enable w ~a: -HCS Host Chip Select +HRD/-HWR ~ §::c -DT/-OE 1 Readylrransfer Acknowlege -PMHOLD (4111A) (4mA) Page Mode Hold Data Buffer Output Enable Vertical Blank ::'ASHIF.T 't~ :: :2}· Address Shift Horizontal Blan -BGACK (4mA) +BG Bus Grant Acknowlege Composite Syn< Bus Grant Input C…

HaRivar Mercury 24 Specification Revision XA1 January 20, 1993 Jeff Tingley RasterOps Corporation PART # 0002-0499 CONFIDENTIAL Mercury 24 January 20, 1993 1.0 Introduction This document establishes the physical and electrical characteristics for the Mercury 24, The Mercury 24 is a high resolution, graphics display board for the Macintosh computer. The Mercury 24 occupies one NuBus slot in the Macintosh. It is capable of six pixel depths, multiple resolutions, and has a QuickDraw accelerator. The connectors for a MIPS co-processor or DSP based daughter board are also included. A block diagram of the Mercury 24 is shown in Figure 1-1. This document is the property of RasterOps. Reproduction of this document is prohibited. Video System Controller Synes RGS14188 8 (Venus) 3 Latched Address E § oo NuBus Interface $ (Earth) 3 2 NuBus Flash Eprom Le Mercury RGS90392 ColorBoard Data Bus a= [ NuBus Expansion ] } g [Ay 6 5 DRAM Array Display Memory L R-Bus Expansion | (Up to 256 MBytes) 1024 x 1024 x 32 BT9046-110 (4 MBytes) Clock Synthesizer Figure 1-1 Mercury 24 Block Diagram 2.0 Hardware Description 2.1 Features Switchable Resolutions of (Software Selectable stored in EEPROM or Monitor ID Selectable) - 1280 x 1024 (16-bit, 75 Hz Vertical Refresh, Non-interlaced) - 1152 x 870 (75 Hz Vertical Refresh, Non-interlaced) - 1024 x 768 (60,75 Hz Vertical Refresh, Non-interlaced) - 832 x 624 (75 Hz Vertical Refresh, Non-interlaced) - 640 x 870 (75 Hz Vertical Refresh, Non-interlaced) - 640 x 480 (66 Hz Vertical Refresh, Non-interlaced) Confidential Material 2 Mercury 24 January 20, 1993 Pixel Depths of 1, 2, 4, 8, 16, and 24-bits NuBus Block Mode Migst/Slave Compatible ~oe Yam acces) 134.2 Million Color Palette (9 bit DACs) Mercury based QuickDraw Accelerator RS-343 Video Compatible 15-Pin D-Submininature Connector (Same as Apple) Hardware Zoom of 1x, 2x, 3x... to 16x Smooth Pan independent of pixel depth 2.2 Overview The Mercury 24 is a stand alone frame buffer. It can display up to 24-bits per pixel in one of many resolutions. It is capable of integer zoom and implements smooth paning in all bit depths. The DACs are 9-bit instead of 8-bit to allow for gammas up to 2.4 without redundant colors. A Mercury based QuickDraw Accelerator is included for maximum performance. As an added feature, the Mercury 24 also supports an MIPS coprocessor or a DSP based daughter card. 3.0 Technical Data 3.1. Absolute Maximum Ratings Supply Voltage, VCC ......esesssssssesessssessesesssseeeseessesseeeeens 5.25 Volts Operating Ambient Temperature Range ...........:: 0 °C to 60 °C Storage Temperature ..........sscsscseeseees vee -65 °C to 150 °C ICC (Supply Current) 0... cessseesesssssssssssesesssesseseseeseseeeenees 40A @5.25V 3.2 Reference Drawings The following items should be referenced for information on the Mercury 24. Mercury 24 Top Assembly LM 2642 Mercury 24 Schematics 0002-0496-1 1 Mercury 24 PCB Fab 0002-0497 Mercury 24 PCA 0002-0498-10 Mercu…

COLORBOARD 8/24S Specification Revision C1 May 9,1990 Jeff Tingley RasterOps Corporation PART# 0002-0076 8/24SSpecification 1.0 May 21, 1990 Introduction This document establishes the physical and electrical characteristics for the ColorBoard 8/248 System. ColorBoard 8/248, referred to as 8/248 throughout the rest of this document, is a medium resolution, high speed, graphics display system for the Macintosh II, llX, and llCX. The 8/248 occupies 1 Nubus slot. It is capable of five pixel depths and supports interlaced and non-interlaced monitors. A block diagram of the 8/248 is shown in figure 1-1. This document is the property of RasterOps Corporation and is confidential. Reproduction of this document is prohibited. r"". NU BUS ISOLATIO N ~ BUFFERS ~ ADl31.:lll. I"15-PIN DSUB '-"' CONTROL &CLOCKS - r-- NUBUSAND FRAt.E BUFFER CONTROLLING ASIC (NBSC) l CONFIG. ROM (18BITS WIDE) ROM ADD.BUS BT473 RAMDAC ROM ADD. BUS DAC~ r'°"i. RED GREEN BLUE ~ REDDATA GREEN DATA BLUE DATA ROWICOL ADDA. E FRAM BUFFER 1024 512 24 x x PIXEL ....... UNPACKING ASIC ..BED. (VBEC) r.Rl:'l:'l\I .Bl LIE. RED, GREEN, AND BLUE SERIAL DATA ~ClOCK~~] 30.24MHZOR 12.3356 MHZ Figure 1-1 8/248 Block Diagram 2 B/24SSpecification 2.0 May 21, 1990 Hardware Description 2.1 Features Switchable Resolutions of -640 x 480 - 640 x 480 x 30Hz (NTSC Frequencies) - 640 x 480 x 25Hz (PAL Frequencies) Pixel Depths of 1, 2, 4, 8, 24-Bits - 24-Bit Mode is Full Chunky Macintosh II "FAT" and "Skinny" NuBus Compatible 16.7 Million Color Palettes 30.24, 12.3356 MHz and 14.25 MHz (PAL) Video Rates External Genlock capablity Single NuBus Slot Current Consumption of 0.90 Amps at 5 Volts 300 nS Cycle for 24-Bit Pixels RS-343 Compatible 15-Pin D-Submininature Connector (Same as Apple) State of the Art Surface Mount Technology Including two ASICs Supports Nubus Block Mode User Expandable from 8 to 24 Bit Color 2.2 Overview The 8/24S's function is to provide a inexpensive 24-bit solution for the Macintosh user. The 8/24S supports all pixel depths the user could ever need, from 1-Bit for speedy drawing all the way up to 24-Bit for true color reproduction. Added feature include full support of block mode transfers 3 8124SSpecification May 21, 1990 over the Nubus ™and NTSC and PAL frequency compatibility. 3.0 Technical Data 3.1. Absolute Maximum Ratings Supply Voltage, VCC ............................................................... 5.25 Volts Operating Ambient Temperature Range .............................. O°C to 60 °C Storage Temperature ................... .... ................... ........ .... .. .... . -65 °c to 150 °c ICC (Supply Current) ............................................................... 1.5 A @ 5.25 V 3.2 Reference Drawings The following items should be referenced for detailed information on the 8/24S system. 8/24S Top Assembly LM ....................... 8/24S 8/24S Top Assembly Drawing ............ 0002-0066 8/24S Assembly Drawing ......…