I PowerPC™ Microprocessor Common Hardware Reference Platform: I/O Device Reference LICENSE INFORMATION To the extent that Apple Computer, Inc., International Business Machines Corporation, and Motorola, Inc. (referred to as “the creators”) own licensable copyrights in the PowerPC Microprocessor Common Hardware Reference Platform: I/O Device Reference (including accompanying source code samples), the creators grant you a copyright license to copy and distribute portions of this document (including accompanying source code samples) in any form, without payment to the creators, for the purpose of developing original documents, code, or equipment (except integrated circuit processors) which conform to the requirements in this document and for the purpose of using, reproducing, marketing, and distributing such code or equipment. This authorization applies to the content of this specification only and not to the referenced material. This authorization does not give you the right to copy and distribute this document in its entirety. In consideration you agree to include for each reproduction of any portion of these documents or any derivative works the copyright notice as displayed below. You are responsible for payment of any taxes, including personal property taxes, resulting from this authorization. If you fail to comply with the above terms, your authorization terminates. The creators and others may have patents or pending patent applications, or other intellectual property rights covering the subject matter described herein. This document neither grants or implies a license or immunity under any of the creators or third party patents, patent applications or other intellectual property rights other than as expressly provided in the above copyright license. The creators assume no responsibility for any infringement of third party rights resulting from your use of the subject matter disclosed in, or from the manufacturing, use, lease, or sale of products described in, this document. Licenses under utility patents of IBM® in the field of information handling systems are available on reasonable and non-discriminatory terms. IBM does not grant licenses to its appearance design patents. Direct your licensing inquiries in writing to the IBM Director of Licensing, International Business Machines Corporation, 500 Columbus Avenue, Thornwood, NY 10594. Licenses under utility patents of Apple Computer, Inc., that are necessary to implement the specification set forth in this document are available on reasonable and non-discriminatory terms. Apple Computer, Inc. does not grant licenses to its appearance design patents. Direct your licensing inquires in writing to Mac OS Licensing Department, Apple Computer, Inc., 1 Infinite Loop, MS 38-LG, Cupertino, CA 95014. © Copyright Apple Computer, Inc., International Business Machines Corporation, Motorola, Inc. 1996. All rights reserved. Note to U.S. Government Users—Documentation related to restricted rights— Use, d…

R&D University PowerPC Runtime Arch itectu re PowerPC Runtime Architecture, October 14, 192 R&D University PowerPC Runtime Architecture •• • II • Itt t I Alan Lillich Developer Tools Group ( PowerPC Runtime Archttecture Version 1.1 .. _._-_. -" ... __._----- _.--_.___.-_.-___ - - - - _ .--_._. .. .. .. ... .. 1 Day 1 Content . . . .:' . . . . . . ': ....... :: .... ::. :.' · .. .. · .. . .. · ~.:. .... :.~ ::,:., ~':..~.\: . ... . : ~ 'C' :;::. ''- • ',' P_PC Runtime Archlectu.. Version 1.1 • '- • '- • '-'- R&D University Alan Lilich " Apple Confidential 11·10--112 2 2 Schedule for Today c . .. ....... . . First Day of Course a I lUlU urluan II I II UDDUDI I II r • Background Information • Program Components • Global Addressing • Stack Frames • Calling Conventions p""""pc Runtime Architecture Version 1.1 c R&D University Alan Lillich - Apple Confidential 11·1D--92 3 3 Background Information .' • Hardware Architecture - Review features that influence software architecture • Miscellaneous - Software architecture derived from AIX - Assembly programmers must do what compilers do! - We're only talking about 32-bit software • Special code can take advantage of 620 • No fully 64-bit O/S planned yet P ......rPC Runtime Architecture R&D Unive..iy Version 1.1 Alan LiNich " Apple Confidential 11-10-·92 4 4 ,. Background Information c' . .. .. Definitions • Effective Address: 3~b;-t-5 - The "register size" addresses used by PowerPC software. • Virtual Address: L '.1- '80 ~ - A "large" address used by PowerPC hardware during address translation. • Volatile Register: - A register whose contents need not be the same on return from a call as before. PowerPC Runtime Archftec:ture V.aion 1.1 R&D UnivelSiIy Alan UHich It Apple Confidential 11·10--92 5 5 CPU Architecture Key Instruction Set Features alia IIU II UIIUIIUI I I 11111111111111 "nann I I a I 1111111 1m III I II I I I • Three basic units => cheap branches • Typical load/store architecture • Generally three register operands • Fixed length instructions - Few memory addressing modes • 32 bit only PowerPC Runlime Architecture Version 1_1 R&D University Alan URich " Apple Confidential 11-10--92 6 6 CPU Architecture . Key Instruction Set Features , , II I I I II 1111 I • Lots of registers - 32 General Purpose (32/64 bit) - 32 Floating Point (64 bit) - 8 Condition Code "Fields" (4 bits: LT, GT, EQ, SO) • A large set of (mostly) reduced instructions • Effective Address versus Virtual Address PowerPC Runtime AR:hilectU18 Version 1.1 R&D University Alan LiRich II Apple Confidential 7 11-10--92 7 CPU Architecture .' . ~v-L*,o........ 5 • Unconditional Branches ~D'J... ~~ ~s - PC relative, 24-bit ~diate displacement (+32MBr • Conditional Branches - PC relative, 14-bit immediate displacement (+32KB) - Indirect through Link or Count Register • Displacements - Are signed and in words (inst…

Page - 1 Common Hardware Reference Platform Architecture Version 1.0 Change Notice October 2, 1996 Apple/IBM/Motorola - CHRP Board Apple/IBM/Motorola - CHRP Board 2 This paper presents a chronological list of all changes approved for the published version of the PowerPC Microprocessor Common Hardware Reference Platform: A System Architecture (CHRP). These changes are approved by the CHRP Board. These changes will be incorporated into the next version of the CHRP document at the next printing. Editorial Comments June 6, 1996 The following editorial comments have been received through June 6, 1996. ■ Page xx add a paragraph before the paragraph starting “Sample implemen- tations ...” to describe the use of this material by component manufacturers. “This document is one of those needed by vendors building chips and adaptors for use in these platforms. Component manufacturers must produce components which conform to this architecture.” ■ Change the second paragraph on page xxiii to read “Big-Endian numbering of bytes is used in this document, unless indicated otherwise. Numbering of bits starts at zero for the most significant bit and continues to the least significant bit, unless indicated otherwise.” ■ Change the third paragraph on page xxiii to indicate the table number. “Ty- pographical ... in Table i on page xxiii.” ■ Change the table number on page xxiii to be “Table i.” ■ Change the last sentence in the paragraph and change the list under 2.5.1.4 on page 18. This paragraph should now read as follows: “The description column ... Two documents are referenced extensively using an abbreviation in this description column. The abbreviations are as follows: [20] refers to the PowerPC Microprocessor Common Hardware Reference Platform: I/O Device Reference. Use this document for additional information on the annotated specifications. [23] refers to the Macintosh Technology in the Common Hardware Reference Platform. Use this document for specific physical, timing, and electrical requirements of the annotated specifications.” ■ Remove the two instances of the phrase “(see note 1)” in the Specifications column for the Pointing Device row in Table 2 on page 19. ■ Add the phrase “For 64-bit addressing option in HBs:” to the start of re- quirement 3-5 on page 29 and 227. Apple/IBM/Motorola - CHRP Board 3 Editorial Comments June 6, 1996 ■ Remove a redundant sentence in the last paragraph on page 37. This para- graph should read “Addresses in peripheral I/O Space from BIO+64 KB to BIO + (8MB - 1) are reserved for hardware use. HBs may treat ...” ■ At the bottom of page 37 add a note which should read as follows: “Software Implementation Note: When in the discontiguous I/O mode software should not put out an operation to Peripheral I/O Space which crosses a 32-byte boundary. Results from such operations are undefined.” ■ Change the table reference for requirement 3-18 on page 39 and 230 to “Ta- ble 7 on page 44.” ■ Add a new bullet under “S…

R&D University • Introduction to PowerPC Instruction Set sity Introduction to PowerPC- Instruction Set: Rev 2, 2/93 ~~ 5 'f-Y"Ct_ c'+C) ,~.:z:::~.-o '"\-<."> P (; «.J'-€Jl Pc ~ 1!:::1I-..~1I'S PowerPC ( PowerPC Architecture Overview ~..J Book I - User Instruction Set Branch Unit Fixed Point Unit Floating Point Unit Book 11- Virtual Environment Book III - Operating Environment The First PowerPC Chips (Book IV) 1P'o~ 1!:::11-.. ~II'S PowerPC PowerPC Architecture Overview Book I - User Instruction Set Branch Unit Fixed Point Unit Floating Point Unit Book II - Virtual Environment Book 111- Operating Environment The First PowerPC Chips (Book IV) ~ 1!:::11-..~ RISC History and Lineages IBM 801 Branch Processor -> RT -> POWER -> PowerPC Berkeley RISC Register Windows -> 29K, SPARC Stanford MIPS -> MIPS, 88K, Alpha, ARM ~~.~u. • We'll look at several of these characteristics with real RiSe examples. Rise Fundamentals PipeLined Programming Model Compiler hae Substantial Effect on Performance Simple, Fixed Instruction Formats 10Cycie Decode, Large Number of Registers Simple Semantics 10Cycie Execution Stage Provide ·Prlmitlves- to Complier Only Loads & Stores Reference Memory LoadlStore Architecture Minimize Use of Critical Resources •. g., Condition Cod.s Caches Ron H......... 2iMI3 ~~.~ Instruction Execution Model ( ~-- F 1. Fetch Next Instruction 0 2. Decode Instruction, ~calculate Addresses, etch Operands, etc.) X 3. Perform Operation W 4. Write Back Results 5. Goto Step 1. Ron H.....-uno 21M3 ~1ClIme·~NI Ideal Instruction Sequence Instructions Require only 1 Clock per Stage 1. Fetch Next Instruction F 2. Decode Instruction, Calculate Addresses, Fetch Operands 0 3. Perform Operation X 4. Writ.Back Results W 11 12 11 11 5. Goto Step 1. Clocks ( "an H.......... IItIt3 • Cycle Time of ,each Stage is the same. PlpeLinlng Increase Throughput by Keeping Resources Busy ( Implement Each Instruction Stage by a Separate Unit - Pipe Stage. Each Pipe Stage Operates on a DIHerent Instruction In a Cycle Don't Wait for An Instruction to Complete before Starting the Next Does Not Reduce Latencyl! ~WMI'IPC~-~11liI PlpeLined Instruction Sequence Instructions Require only 1 Clock per Stage ( 1. Fetch Next Instruction F 2. Decode Instruction, Calculate Addresses, Fetch Operands 0 3. Perform Operation X 4. WriteBack Results W 11 12 13 14 15 11 12 13 14 11 12 13 11 12 5. Goto Step 1. CI_ ~ Ron H...,..... 2ItIU ~~-~ Instruction Formats ( tid b ¥ !-form OP 8-form OP Bol BI D-form OP RxlRA X-form OP RT IRA RB I XOP XO-form OP RTIRA RB fl XOP A-form OP RS IRA RB I RC IXOp~ filaddfl,f2,B,fl M-form OP RS IRA RBI MB I ME ~ Ron H......... 2ItII1 Dise24 Dise14 ~D 1Nl\)tZ addl 1'5,1'4,123 I. 1'5,211(1'4) Imm16 n and r),r4,~ and. rS,r4,~ I .. r),r4,~ fl add rS,r4,~ addeo. r'.r4.rS rl_ rS,r4,~,2II,31 ~ ~1C1JSJM-~ Branches - The Problem Branches Leave "Bu…

I PowerPC™ Microprocessor Common Hardware Reference Platform: A System Architecture Personal Use Copy - Not for Reproduction LICENSE INFORMATION To the extent that Apple Computer, Inc., International Business Machines Corporation, and Motorola, Inc. (referred to as “the creators”) own licensable copyrights in the PowerPC Microprocessor Common Hardware Reference Platform: A System Architecture (including accompanying source code samples), the creators grant you a copyright license to copy and distribute portions of this document (including accompanying source code samples) in any form, without payment to the creators, for the purpose of developing original documents, code, or equipment (except integrated circuit processors) which conform to the requirements in this document and for the purpose of using, reproducing, marketing, and distributing such code or equipment. This authorization applies to the content of this specification only and not to the referenced material. This authorization does not give you the right to copy and distribute this document in its entirety. In consideration you agree to include for each reproduction of any portion of these documents or any derivative works the copyright notice as displayed below. You are responsible for payment of any taxes, including personal property taxes, resulting from this authorization. If you fail to comply with the above terms, your authorization terminates. The creators and others may have patents or pending patent applications, or other intellectual property rights covering the subject matter described herein. This document neither grants or implies a license or immunity under any of the creators or third party patents, patent applications or other intellectual property rights other than as expressly provided in the above copyright license. The creators assume no responsibility for any infringement of third party rights resulting from your use of the subject matter disclosed in, or from the manufacturing, use, lease, or sale of products described in, this document. Licenses under utility patents of IBM® in the field of information handling systems are available on reasonable and non-discriminatory terms. IBM does not grant licenses to its appearance design patents. Direct your licensing inquiries in writing to the IBM Director of Licensing, International Business Machines Corporation, 500 Columbus Avenue, Thornwood, NY 10594. Licenses under utility patents of Apple Computer, Inc., that are necessary to implement the specification set forth in this document are available on reasonable and non-discriminatory terms. Apple Computer, Inc. does not grant licenses to its appearance design patents. Direct your licensing inquires in writing to Mac OS Licensing Department, Apple Computer, Inc., 1 Infinite Loop, MS 305-1DS, Cupertino, CA 95014. © Copyright Apple Computer, Inc., International Business Machines Corporation, Motorola, Inc. 1995. All rights reserved. Note to U.S. Government Users—Docu…

R&D University Porting to PowerPC ( sitv ," { ... PowerPC .dl ij''":oftllb ,.";' : .,.J:>£,--:1 :.' '>~", :)dt\Ulration strategies for PowerPC ' . ,. , ..' . d'C ,an4'~;Th1i;-,b~YF;become the ~~9h~p()~~~§ this decade, and most of the development tools that are available are geared towards these languages. Because of this, the earliest PowerPC development tools will be oriented towards C and C+ + programmers. However, since many ,". devel~ve WtlitmrlttlllffiIlflmductsirt Wt~es.()ther than C or C+ +, we'll take a quick look at theii:i{iptions WffioVing11OipowerPC. ' '. 811'r g.lig;,_"j:)IDilor-:;n, '. , li1 ~)!i;, Gii'. ,., .. ).)" _ . Pascal Development ,')JHJO?, I"IJ ~i;' Pascal developers have a{ew:~when ~~ng-the.ir code to PowerPC: - Wai~ for:a third-party Pasca[compiler~MetroWer~ is producing a Pascal compilers for PowerPC. ~:~b::~~~~~!~j~~~~~.oo:~t~p~:who - Re~ U'fC or C+ +: This approach, while potentially difficult, gives you the widest range of po :::.;Wityloptions to PowerPC and other p1a,tfonJ1S (ifyou should ever choose to go crosspla tp', '; 1;HH rol - uset~:;:;as.ql t~~conversion tool: Sierra ~~are has produced "~2C", which converts P~ or Object PjlSCal to QC+ +. Several groups Wlthm Apple have used thIS too~ and most of them didn't like~W~fe ~ loo~~g for a better solution. , ..... ' uJ~h~I;j~!~~Hd:_:(a spin-off of Bell Labs) makes "FlashPort", a tool which treats your compiled application as the input to a compiler which emits PowerPC object code. This yields an application which is faster than a strictly emulated 680xO application, but somewhat slower and larger than an applkation re-compiled for PowerPC from its original sources. " - Port as ~tich as ~ible/and emulate non-portable parts via Mixed mode: This is a reasonable ) ~atq~gy.~rtt}t.~a~~me parts of your code that are not processor intensive and which would be (,~~4hp:~()!f/«Q~ever, remember that you will not get the full performance benefits that a .lm~re '&rWplele pbhmg job would yield. Assembly-Language Development Assembly-language programmers cannot simply re-compile for PowerPC; some sort of porting will be required Our recommendation is that you re-write your assembly code as portable C source code. While many assembly language programmers feel that this is a poor chOice, the design of the PowerPC Macintosh removes many of the reasons that developers write in assembly language. The 4 major reasons developers write in assembly language are 1) speed, 2) linking different calling conventions together, 3) addressing custom hardware installed in a particular machine, or 4) a need to jump to a particular routine instead of using a subroutine call. We'll look at how the PowerPC programming model addresses each of these issues. Migration Strategies for PowerPC Page 1 • The first case, speed, should be handled adequately by the optimizing Ccompilers. Creating optimized code for the PowerPC is no easy feat, and it is easy to overlook one rule or another wh…

PowerPC Microprocessor CHRP binding 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 1 PowerPC™ Microprocessor Common Hardware Reference Platform (CHRP™) System binding to: IEEE Std 1275-1994 Standard for Boot (Initialization, Configuration) Firmware Revision: 1.7 [Approved Version] Date: September 23, 1996 September 23, 1996 Revision 1.7 [Approved Version] 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 September 23, 1996 Revision 1.7 [Approved Version] PowerPC Microprocessor CHRP binding PowerPC Microprocessor CHRP binding 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 3 Purpose of this PowerPC Microprocessor CHRP™ System binding This document specifies the application of Open Firmware to a PowerPC Microprocessor CHRP System, including requirements and practices to support unique hardware and firmware specific to the platform implementation. The core requirements and practices specified by Open Firmware must be augmented by system-specific requirements to form a complete specification for the firmware implementation of a PowerPC Microprocessor CHRP System. This document establishes such additional requirements pertaining to the platform and the support required by Open Firmware. Task Group Members The following individuals were members of the Task Group that produced this document: Rob Baxter, Motorola® Mitch Bradley, FirmWorks Steve Bunch, Motorola Bob Coffin, IBM® (editor) Ron Hochsprung, Apple® John Kingman, IBM Dr. Luan Nguyen, IBM John O’Quin, IBM Andy Rawson, IBM Mike Segapeli, IBM Trademarks The following terms, denoted by a registration symbol (®) or trademark symbol(™) on the first occurrence in this publication, are registered trademarks or trademarks of the companies as shown in the list below: Trademark Company AIX™ International Business Machines Corporation Apple Apple Computer, Inc. CHRP Apple Computer, Inc. Ethernet™ Xerox IBM International Business Machines Corporation Microsoft® Microsoft Corporation Macintosh™ Apple Computer, Inc. September 23, 1996 Revision 1.7 [Approved Version] 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 PowerPC Microprocessor CHRP binding Mac™ OS Apple Computer, Inc. Motorola Motorola, Inc. PowerPC International Business Machines Corporation Windows NT™ Microsoft Corporation Revision History Revision 0.1 07/27/95 Initial draft; limited distribution to CHRP AIM(Apple, IBM & Motorola) Team Revision 0.2 08/15/95 Initial draft with distribution to CHRP AIM Team for review. Revision 0.3 09/08/95 Distribution to CHRP AIM Team for review…

Software Development Training • C++ Part II .~ ..... " i;:~nware Development Training c++ Part II, Rev. 7192 I c++ Part 2 f '. Copyright © 1992 Neal Goldstein and Apple Computer, Inc. All Rights Reserved. No part of the written course material may be reproduced in any form or by any means without permission in writing from Neal Goldstein or Apple Computer. The sample programs and source code may be llsed by attendees of this seminar, or purchasers of these seminar notes, for their own personal use. The programs and/or source code may not be used for commercial purposes without permission in writing from Neal Goldstein or Apple Computer. All attempts are made for the information presented in this seminar to be accurate and correct to the best of our knowledge, however Neal Goldstein, Apple Computer, or the instructor cannot be held liable for any incomplete or erroneous information. If you find anything to be misleading or incorrect, please notify Neal Goldstein or Apple, which will make every effort to correct and update future releases. Apple, the Apple Logo, AppleLink, Macintosh, and MacApp are registered trademarks of Apple Computer, Inc. © 1992 Ncal Goldstein and Apple Computcr, Inc. Introduclion 1 .Developed By: .~ - ;~r ··Neal Goldstein ........ ..".,. , " ~ . ~ ... ,. " Neal Goldstein :Design . : ·-659 Tennyson Avenue ?:; . Palo Alto; CA 94301 I' of ! " •" J • ,. ~,..,. , ,. ,' . ~',. , , ... , ..... ~; ·(415) 327-4565 " AppleLink D077} ·1; , ..•• © 1992 Neal Goldstcin and Apple Computcr, Inc Introduction 2 ,./ 'j I Table of Topics <! \ ' Section 1 Introduction : ~. if:, :"1 Introduction .......................................................................................... 1 Class goals ..................................................:·...................... ~-:.:........•:...... 4 ' C++ on the Macintosh ............................................................................. 6 . C++ design goals .................. , ................................ .... ':. j • !.~ ••••• , . : •••• i \ ..'" .-:; •.••• 8 Group discussion ........................................................................ :......... 10 The most difficult things to do using C++. What is (still) hardr (.-" 1;" .' <", Compiler and linker error messages to watch out for ............. :.... :........... ~; ......... 11 Memory allocation ......................................... ; ..,~,.~. ..i::.;;.: .. .... ;.!o',\ .... :.L:':~i'" .13 Creating objects ................................................................................... 14 FCunction overloading ................................................... ~ .......... ..j .... ..'.~{; .... 15 tenns ............................................................................................. 17 ~ Naming conventions ...................................................... :·:~:~ ................... 18 Labs .........................................................…