.Page
;++
;		Interface Routines
;--

SelSide	.Equ *
	Ldx	#0
	Lda	#20
	Bit	IIob+Side
	Beq	SetSel
	Inx

SetSel	.Equ *
	Lda	Ca0+High
	Lda	Ca1+High
	Lda	Side0Sel,x
	Txa
	Rts

SetLow	.Equ *
	Ldx	#Low			; set Side Select line low
	Beq	SetSel

SetHigh	.Equ *
	Ldx	#High			; Set line high
	Bne	SetSel

ReadWp	.Equ *
	Jsr	SetHigh
RdS2	Lda	Ca1+Low
RdS1	Lda	Ca2+Low
ReadIt	.Equ *				; Read sense bit & rotate into ccC
	Lda	Q6H			; Ensure state machine in proper state
	Lda	Q7L			; Read sense daata into bit 7
	Asl	A			; Move bit 7 into carry
	Rts

ReadIndx	.Equ *
	Clc
Rid	.Equ *
	Jsr	SetHigh
	Lda	Ca0+Low
	Bcc	RdS1			; set Ca2 = 0
	Bcs	RdS2			; set Ca1 & Ca2 = 0

ReadDip	.Equ *
	Sec
	Bcs	Rid

DoStrb	.Equ *
	Sta	LStrb+High
	Nop
	Nop
	Sta	LStrb+Low
	Rts

TrMtOff	.Equ *				; Will turn motors off
	Sta	Ca2+High
	Lda	#00
	Beq	TurnMtr

TrMtrOn	.Equ *				; Will turn the Sony motor on
	Sta	Ca2+Low
	Lda	#0FF

TurnMtr	.Equ *
	Sta	MtrOn			; Set state register in Ram
	Jsr	SetLow			; Set side select line low
	Sta	Ca0+Low
	Jmp	DoStrb

TMOn	.Equ *				; Turn on motor & setup for tach reading
	Jsr	TrnMtrOn			; will leave Ca0 = 0
	Lda	#80.			; 400(5*80) msec constant
	Jsr	Wait
SetTach	.Equ *
	Jsr	SetHigh			; set Side Select = 1 for Tach input
	Lda	Ca2+Low			; '10011' for tach mode
	Rts

SetDrexX	.Equ *				; use value in Xreg for direction
	Stx	Direct
SetDrct	.Equ *
	Jsr	SetLow			; set Side Select line low
	Sta	Ca0+Low
	Sta	Ca1+Low
	Ldx	Direct			; 0 or 1 for offset of direction
	Sta	Ca2,x
	Jmp	DoStrb

DoStep	.Equ *
	Lda	#1
	Sta	Temp1			; Try twice
	Jsr	SetLow			; Set Side Select line low
	Sta	Ca1+Low
	Sta	Ca2+Low
	Jsr	DoStrb
$10	Jsr	WaitAlt			; Wait 12 ms for /Step to go high
	Jsr	ReadIt			; ccC = /Step -- 0 = low & 1 = high
	Bcs	DoStDone			; /Step is high so all is cool
	Lda	#StepErr
	Sta	Iob+SeekErr		; For external debugging aid ( FCC01B )
	Dec	Temp1
	Bpl	$10			; wait another 12 ms
DoStDone	.Equ *				; fall through and exit w no error
	Rts

DoSeek	.Equ *
	Jsr	SetDrct			; Set the direction
$23	Jsr	DoStep
	Dec	StpAmt			; Count down the number of steps to take
	Bne	$23			; Exit upon reaching zero
	Rts

SetSpeed	.Equ *
	Jsr	TrkClss			; Return w/ "Y" = class of IIob+Track
SetSpdy	.Equ *				; already has "y" = track class
	Sty	CurClass
	Lda	MSpdTbl,y
	Sta	PwmReg
	Rts

SetRMode	.Equ *
	Jsr	SelSide			; use value in IIob+Side to set proper side
	Sta	Ca0+Low
	Sta	Ca1+Low
	Sta	Ca2+High			; 'x100' is input to MCI PAL on Sony
	Rts

UnClamp	.Equ *
	Jsr	SetLow
	Sta	Ca2+High			; '0111'
	Lda	LStrb+High
	Lda	#150.			; 3/4 sec (200*5 usec ) delay for ejection
	Jsr	Wait			; Will wait & return w/ carry cleared
	Lda	LStrb+Low
	Lda	#0
	Sta	Clamped			; Tell me disk is no longer clamped
	Clc
	Rts

HardInit	.Equ *				; Initialize hardware -- PWM & Iwm
	Ldx	#0e	
$7	Sta	IOSpace,x			; Reset all IWM internal latches to zero state
	Dex	
	Dex
	Bpl	$7			; Loop 8 times
	Lda	#202.
	Jsr	Wait			; wait for 1.01 sec for timer to expire

	Ldx	#0			; $10000 times before timeout
	Stx	Temp1

$15	Dex	
	Bne	$30
	Dec	Temp1
	Beq	HardAbort			; If timeout then IWM is out to lunch

$30	Lda	Q6H			; Put IWM state machine into SENSE mode
	Lda	Q7L			; Read status data
	Tay				; Save IWM's status information
	And	#20			; Test bit #5
	Bne	$15			; Wait for bit #5 to be clear ( 0 )

	Tya				; Restore status info
	And	#IWMMode			; Mask off unneeded bits

	Cmp	#IWMMode			; look for proper bits to be set
	Beq	$45			; if same then all is OK


	Lda	#IWMMode			; Asynch, 8 MHz, latch, 2 usec calls, no timer
	Sta	Q7H			; Setup to proper Sony mode
	Lda	Q7L			; back to SENSE mode
	Jmp	$15			; Walk through & make sure it works

$45	Sta	DrEna+High		; Select drive 1
	Sta	MtEna+On			; Now enable that drive for ever and ever
	Ldx	MSpdTbl			; Default speed code for track 0
	Stx	CntEna+Low		; Enable counter/comparator
	Stx	PWMReg			
	Stx	PwmEna+High		; Enable output of Pwm pulse
	Rts

HardAbort	.Equ *
	Lda	#IWMError			; Fatal error w/ IWM -- does not respond
	Sta	Iob+ErrStat
	Jmp	FatalErr			; Abort and never return

ChkDrv	.Equ *				; Check for drive connected and number of sides
	Lda	#1
	Sta	Iob+NoSides		; Assume single sided drive
	Jsr	SetLow			
	Sta	Ca2+High			; '0111'
	Sec				; Assume no drive exists
	Lda	Q7L			; High bit = status
	Bmi	$30			; If bit7 = 1 then no drive is connected
	Dec	DrvConn			; Set drive connected flag
	Clc	
	Sta	Ca0+Low			; Assume only single sided
	Ldx	Q7L
	Bpl	$23			 
	Inc	Iob+NoSides		; 2 = double sided drive
	Ora	#20			; Set double sided flag for format field
$23	Sta	FmtType			; For use in formatting
$30	Rts				; ccC = 0 ==> drive connected

.Page
;--
;
;				De-Nibble Table
;
; 7-Bit to 6-Bit 'Denibbleze' table (16 sector format).
; Valid codes 096 to 0FF only.
; Codes with more than one pair of adjacent zeroes or with no adjacent ones
; (except Bit 7) are excluded.
;
;++

	.Org	1196
DNibl	.Equ *-96
	.Byte 000,001,098
	.Byte 099,002,003
	.Byte 09C,004,005
	.Byte 006,0A0,0A1
	.Byte 0A2,0A3,0A4
	.Byte 0A5,007,008
	.Byte 0A8,0A9,0AA
	.Byte 009,00A,00B
	.Byte 00C,00D,0B0
	.Byte 0B1,00E,00F
	.Byte 010,011,012
	.Byte 013,0B8,014
	.Byte 015,016,017
	.Byte 018,019,01A
	.Byte 0C0,0C1,0C2
	.Byte 0C3,0C4,0C5
	.Byte 0C6,0C7,0C8
	.Byte 0C9,0CA,01B
	.Byte 0CC,01C,01D
	.Byte 01E,0D0,0D1
	.Byte 0D2,0AF,0D4
	.Byte 0D5,020,021
	.Byte 0D8,022,023
	.Byte 024,025,026
	.Byte 027,028,0E0
	.Byte 0E1,0E2,0E3
	.Byte 0E4,029,02A
	.Byte 02B,0EB,02C
	.Byte 02D,02E,02F
	.Byte 030,031,032
	.Byte 0F0,0F1,033
	.Byte 034,035,036
	.Byte 037,038,0F8
	.Byte 039,03A,03B
	.Byte 03C,03D,03E
	.Byte 03F

.IF     EXTERNAL = 1
        .NOLIST
        .ENDC

        .PAGE
        .ABSOLUTE	        ;makes listing look nicer
        .PROC   LISAROM,0

        .ORG    0	        ; ORG'ED AT 0 BUT RUNS AT $00FE0000

;  Reset vectors here to pick up SP and PC values

BASE
        .WORD   $0000	        ;initial SP
        .WORD   STKBASE

        .WORD   ROMSLCT	        ;initial PC (assumes use of MMU reg 127)
        .WORD   BEGIN

;  Set up next locations for exception vectors

BUSVCT  .WORD   ROMSLCT		  ; BUS ERROR VECTOR
        .WORD   EXCPERR
ADRVCT  .WORD   ROMSLCT		  ; ADDRESS ERROR
        .WORD   EXCPERR
ILLVCT  .WORD   ROMSLCT		  ; ILLEGAL INSTRUCTION
        .WORD   EXCPERR
DIV0VCT .WORD   ROMSLCT		  ; DIVIDE BY ZERO ERROR
        .WORD   EXCPERR
CHKVCT  .WORD   ROMSLCT		  ; CHK INSTRUCTION
        .WORD   EXCPERR
TRAPVCT .WORD   ROMSLCT		  ; TRAPV INSTRUCTION
        .WORD   EXCPERR
PRIVCT  .WORD   ROMSLCT		  ; PRIVILEGE VIOLATION
        .WORD   EXCPERR
TRCVCT  .WORD   ROMSLCT		  ; TRACE OPERATION
        .WORD   EXCPERR
L10VCT  .WORD   ROMSLCT		  ; OPCODE 1010 DETECTED
        .WORD   EXCPERR
L11VCT  .WORD   ROMSLCT		  ; OPCODE 1111 DETECTED
        .WORD   EXCPERR

;------------------------------------------------------------------
;  Exception and interrupt vector handler for ROM - resets SP and
;  tries a restart
;------------------------------------------------------------------

EXCPERR MOVEA   #STKBASE,SP     ;reset stack ptr
        CLR.L   D7	        ;clear error indicator		        CHG004
        BRA     ROMTST	        ;and restart diags		        CHG004

        .PAGE

;--------------------------------------------------------------------
;  Subroutine for saving registers and stack pointers
;--------------------------------------------------------------------

SAVEREGS
        MOVE.L  SP,SUPSTK       ;save sup stack ptr
SAVEREG2
        MOVE.L  A6,A6SAV        ;save other regs (that aren't reset)
        MOVE.L  USP,A6
        MOVE.L  A6,USPSAV
        MOVE    #A6SAV,A6       ;set ptr for saving regs
        MOVEM.L D0-D7/A0-A5,-(A6)
        RTS

;  use spare bytes for message

SVCMSG  .ASCII  'SERVICE MODE'  ;				        RM000
        .BYTE   0	        ;				        RM000

        .ORG    $60

;  The next set of vectors cover spurious and autovector interrupts

SPURVCT .WORD   ROMSLCT		  ; SPURIOUS INTERRUPT
        .WORD   EXCPERR
LVL1VCT .WORD   ROMSLCT		  ; INTERNAL I/O INTERRUPTS (DISK,VERT TRACE,ETC.)
        .WORD   EXCPERR
LVL2VCT .WORD   ROMSLCT		  ; KEYBOARD INTERRUPT
        .WORD   EXCPERR
LVL3VCT .WORD   ROMSLCT		  ; I/O SLOT 2 INTERRUPT
        .WORD   EXCPERR
LVL4VCT .WORD   ROMSLCT		  ; I/O SLOT 1
        .WORD   EXCPERR
LVL5VCT .WORD   ROMSLCT		  ; I/O SLOT 0
        .WORD   EXCPERR
LVL6VCT .WORD   ROMSLCT		  ; RS-232
        .WORD   EXCPERR
LVL7VCT .WORD   ROMSLCT		  ; NMI
        .WORD   NMIEXCP		  ;				        RM010

        .IF     EXTERNAL = 1
        .LIST
        .ENDC

        .PAGE
        .ORG    $80
;-------------------------------------------------------------------------
;  Jump Table for calling by external routines
;-------------------------------------------------------------------------

JMPTBL
        JMP     DORESET	        ;go to restart point		        RM000
        JMP     INITMON	        ;jump to ROM Monitor

        .IF  USERINT = 0
        JMP     DSPMSG	        ;display a message
        .ELSE
        JMP     CONVRTD5        ;convert row ptr and display message
        .ENDC

        JMP     WRTMMU	        ;write to set of MMU registers
        JMP     PROREAD	        ;Profile read a block routine
        JMP     TWGREAD	        ;Twiggy read a sector routine

        .IF  DIAGS = 1
        JMP     RAMTEST	        ;basic memory test
        NOP		        ;				        CHG015
        RTS		        ;				        CHG015
        NOP		        ;				        CHG015
        RTS		        ;				        CHG015
        .ELSE
        NOP
        RTS
        NOP
        RTS
        NOP
        RTS
        .ENDC

        JMP     READMMU	        ;read MMU registers
        JMP     COPSCMD	        ;Send COPS command

        .IF  DIAGS = 1
        JMP     READCLK	        ;Read clock setting
        .ELSE
        NOP
        RTS
        .ENDC

        JMP     DSPDEC	        ;display hex error code in decimal
        JMP     CONSET2	        ;for setting contrast
        JMP     TONE	        ;to beep speaker
        JMP     VFYCHKSM        ;verify checksum

        .IF  ROM4K = 0
        JMP     WRTSUM	        ;rewrite parameter memory	        CHG017
        JMP     RDSERN	        ;go read system serial #
        .ENDC

;******************** Loop point for ROM test failure ********************************

SPIN    BRA.S   SPIN	        ;hang system				        CHG007

;*************************************************************************************

        .IF     EXTERNAL = 1
        .NOLIST
        .ENDC

;----------------------------------------------------------------------------
;  NMI Exception Handler						        RM010
;----------------------------------------------------------------------------

NMIEXCP CLR.B   SETUP	        ;enable memory access			        RM010
        BTST    #1,STATREG      ;parity error?				        RM010
        BNE.S   @1	        ;skip if not to ignore			        RM010
        MOVE    MEALTCH,ADRLTCH ;save address if yes			        RM010
        TST.B   PAROFF	        ;and toggle to clear error bit		        RM010
        TST.B   PARON	        ;					        RM010
@1      TST.B   SETUPON	        ;return to SETUP state			        RM010
        RTE		        ;					        RM010

        .PAGE
;----------------------------------------------------------------------------
;  First do "warm-start" no reset check - scan I/O MMU regs to see if set up
;----------------------------------------------------------------------------

BEGIN
        .IF     NORESET = 1
        MOVE    MMU126L,D0      ;check reg 126 for special I/O space
        ANDI    #$0FFF,D0       ;ignore don't care bits
        CMPI    #IOLMT2,D0      ;for no reset, 126L = $x901  (x = random value)
        BNE.S   BEGIN2	        ;skip if not set up
        ANDI    #$0FFF,MMU126B  ;else also check 126B = $x000
        BNE.S   BEGIN2

;  Check OK - set MMU for ROM access and change SETUP before vectoring

        MOVE    #MEMLMT,MMU0L   ;set low memory for r/w (to save regs,etc.)
        MOVE    #IOLMT2,MMU126L ;set for I/O space access (reset value)
        MOVE    #SPLMT,MMU127L  ;set access for ROM space
        MOVE    #0,MMU127B
        CLR.B   SETUP	        ;enable memory access

        MOVE.L  SP,SUPSTK       ;save supervisor stack ptr
        MOVEA   #STKBASE,SP     ;move stack pointer for ROM use
        BSR.S   SAVEREG2        ;save other registers

;  Restore ROM Monitor environment

        BSR4    CONSET	        ;go set default contrast
        SUBA.L  A2,A2	        ;set for no icons
        CLR.L   D0	        ; error codes
        SUBA.L  A3,A3	        ;  or messages
        BRA     INIT1	        ;exit directly to monitor (avoid resaving regs)

        .ENDC

;-------------------------------------------------------------------------
;  Do second warm-start check to see if contrast should be reset
;-------------------------------------------------------------------------

BEGIN2  CLR.L   D7	        ;clear for error use
        MOVE    MMU127L,D0      ;check reg 127 for ROM space
        ANDI    #$0FFF,D0       ;ignore don't care bits
        CMPI    #SPLMT,D0       ;expect 127L = $xF00  (x = random value)
        BNE.S   ROMTST	        ;skip if not
        ANDI    #$0FFF,MMU127B  ;else check if 127B = $x000
        BNE.S   ROMTST

;  Check OK - set MMU for I/O and ROM access and go set contrast

        BSET    #WRMSTRT,D7     ;set warm start indicator
        MOVEQ   #0,D0	        ;clear for use
        MOVE    #IOLMT,MMU126L  ;set access for I/O space
        MOVE    D0,MMU126B
        MOVE    #SPLMT,MMU127L  ;set access for ROM space

BEGIN3  RESET		        ;ensure clean I/O state for "warm-start"

        .IF  NEWLISA = 1
        BSR4    CONOFF	        ;and go disable contrast
        .ELSE
        BSR4    CONSET	        ;go set default contrast
        .ENDC


        .PAGE
;-------------------------------------------------------------------------
;  Start diagnostics - do ROM checksum test first; expected result = 0
;-------------------------------------------------------------------------

ROMTST
        .IF  DIAGS = 1

        CLR.L   D0	        ;clear for checksum use
        LEA     BASE,A0	        ;init ROM address ptrs
        LEA     LAST,A1
DOSUM   ADD     (A0)+,D0        ;read location and add to sum
        ROL     #1,D0	        ;rotate to catch multiple bit errors
        CMPA.L  A0,A1	        ;loop until done
        BNE.S   DOSUM
        ADD     (A0)+,D0        ;add checksum word
        BNE     SPIN	        ;loop if error			        CHG007
        TST.L   D7	        ;in loop mode?
        BMI.S   ROMTST	        ;restart test if yes

        .ENDC
        .PAGE
;----------------------------------------------------------------------------
;  Next do read/write and address test of MMU supervisor regs
;  Register Usage (by this routine and/or its subroutines):
;       A0 = MMU reg pointer	        D0 = test pattern
;       A1 = last MMU limit reg addr    D1 = contents read from MMU reg
;       A2 = MMU address increment      D2 = OR mask of results
;       A3 = last MMU base reg addr     D3 = pattern expected at last error
;       A4 = used for return address    D4 = final value for MMU reg
;       A5 = MMU address of last error  D5 = unused
;       A6 = used for return address    D6 = unused
;       A7 = stack pointer	        D7 = error indicator (0 = R/W error)
;----------------------------------------------------------------------------

MMUTST
        .IF     DIAGS = 1
        BSR4    MMUINIT	        ;initialize test variables
        BSR6    MMURW	        ;and go do read/write test
        BNE.S   MMUERR	        ;abort if error

        BSRS4   MMUINIT	        ;reinitialize
        BSR6    MMUACHK	        ;and do address test
        BNE.S   @2	        ;skip if error
        BRA     SETMMU	        ;else go do initial MMU setup
@2      NOT     D7	        ;set address error indicator

        .PAGE
;----------------------------------------------------------------------------
;  The following code is used to toggle every address and data line
;  going to the MMU if an error in the MMU context 0 tests is found.
;  Reset signals indicate read/write or addressing error.
;----------------------------------------------------------------------------

MMUERR  TST     D7	        ;check error type
        BEQ.S   @2
        RESET		        ;two reset signals for address error
@2      RESET		        ;only one for R/W error

;  Toggle every data and address bit

MMULP   MOVE.L  #$00028000,A0   ;set MMU limit reg start address
        MOVEQ   #1,D1	        ;and starting data pattern
        MOVEQ   #7,D2	        ;and loop count
        BSRS4   TSTLOOP	        ;go toggle for limit regs
        MOVE.L  #$00028008,A0   ;set MMU base reg start address
        MOVEQ   #5,D2	        ;and loop count
        BSRS4   TSTLOOP	        ;go test base regs

        BRA.S   MMUERR	        ;and loop indefinitely

;  Subroutine to do reg testing

TSTLOOP MOVE.L  A0,D0	        ;save starting address
REGTST  MOVE    D1,(A0)	        ;do write
        MOVE    (A0),D3	        ;then read
        LSL     #1,D1	        ;update pattern
        SWAP    D0	        ;get address
        LSL     #1,D0	        ;update and restore
        SWAP    D0
        MOVE.L  D0,A0
        SUBQ    #1,D2	        ;loop until done
        BNE.S   REGTST
        RTS4		        ;exit

        .PAGE
;----------------------------------------------------------------------------
;  Subroutine to do initial setup for MMU testing
;----------------------------------------------------------------------------

MMUINIT MOVE    #PATRN2,D0      ;set test pattern
        MOVEQ   #0,D1	        ;clear for result/error use
        MOVEQ   #0,D2	        ; use MOVEQ for speed
        MOVE.L  #ADR128K,A2     ;set up increment value
        ORI     #$0710,SR       ;set extend bit and disable interrupts
        RTS4

        .PAGE
;----------------------------------------------------------------------------
;  Subroutine to do MMU Read/Write Test for all registers in one context.
;  Zero bit set in CCR if no errors.
;----------------------------------------------------------------------------

MMURW   MOVE.L  #MMUSADRL,A0    ;SET MMU LIMIT START ADDR
        MOVE.L  #MMUEADRL,A1    ;SET MMU LIMIT END ADDR
        MOVE.L  #MMUEADRB,A3    ;SET MMU BASE END ADDR

RWCHK1  BSR4    CHKRW	        ;GO DO READ/WRITE CHECK
        NOT     D0	        ;INVERT FOR NEXT PASS
        BSRS4   CHKRW	        ;GO DO AGAIN
RWCHK2  NOT     D0	        ;INVERT BACK TO ORIGINAL PATTERN
        BSRS4   CHKRW	        ;ONE MORE TIME
RWCHK3  ROXL    #1,D0	        ;SET UP NEW PATTERN
        CMPA.L  A0,A1	        ;CHECK IF DONE
        BEQ.S   CHKBASE	        ;IF YES GO CHECK FOR BASE REG TESTING
        ADDA.L  A2,A0	        ;ELSE BUMP MMU ADDR
        BRA.S   RWCHK1

CHKBASE CMPA.L  A0,A3	        ;DONE WITH BASE?
        BEQ.S   @2	        ;EXIT IF YES
        MOVE.L  #MMUSADRB,A0    ;ELSE SET STARTING BASE ADDRESS
        MOVEA.L A3,A1	        ; AND ENDING ADDRESS
        BRA.S   RWCHK1	        ;GO CHECK BASE REGS

@2      TST     D2	        ;check for errors
        RTS6		        ;and exit test

        .PAGE
;----------------------------------------------------------------------------
;  Subroutine to do MMU address check
;  Leaves limit registers with invalid page value, base regs with 0
;----------------------------------------------------------------------------

MMUACHK MOVE.L  #MMUSADRL,A0    ;SET MMU LIMIT START ADDR
        MOVE.L  #MMUEADRL,A1    ;SET MMU LIMIT END ADDR
        MOVE.L  #MMUEADRB,A3    ;SET MMU BASE END ADDR
        MOVE    #INVPAG,D4      ;SET FINAL VALUE FOR LIMIT REGS

ACHK1   MOVE    (A0),D1	        ;READ REG
        EOR     D0,D1	        ;CHECK IF EXPECTED
        ANDI    #$0FFF,D1       ;MASK DON'T CARES
        BNE.S   MADRERR	        ;EXIT IF ERROR

MMUSET  MOVE    D4,(A0)	        ;SET FINAL REG VALUE
        ROXL    #1,D0	        ;SET UP NEW PATTERN
        CMPA.L  A0,A1	        ;CHECK IF DONE
        BEQ.S   ACHK2	        ;IF YES GO CHECK FOR BASE REG TESTING
        ADDA.L  A2,A0	        ;ELSE BUMP MMU ADDR
        BRA.S   ACHK1

ACHK2   CMPA.L  A0,A3	        ;DONE WITH BASE?
        BEQ.S   @2	        ;EXIT IF YES
        MOVE.L  #MMUSADRB,A0    ;ELSE SET STARTING BASE ADDRESS
        MOVEA.L A3,A1	        ; AND ENDING ADDRESS
        MOVEQ   #0,D4	        ;SET FINAL VALUE FOR BASE REGS
        BRA.S   ACHK1	        ;GO CHECK BASE REGS

@2      TST     D2	        ;check for errors
        RTS6		        ;and exit test

;  Handle MMU address error

MADRERR OR      D1,D2	        ;save error bits
        BRA.S   MMUSET	        ; and continue test

        .ELSE
        CLR.L   D2	        ;for error patterns
        BRA.S   SETMMU
        .ENDC

        .PAGE
;----------------------------------------------------------------------------
; Subroutine to do MMU actual read/write
;----------------------------------------------------------------------------

CHKRW   MOVE    D0,(A0)	        ;do write
        MOVE    (A0),D1	        ;read back
        EOR     D0,D1	        ;compare
        ANDI    #$0FFF,D1       ;mask don't cares
        BNE.S   RWERR	        ;skip if error
        RTS4		        ;else return

;  Error collection

RWERR   OR      D1,D2	        ;save error bits
        RTS4		        ;and return

        .PAGE
;--------------------------------------------------------------------------
;  Now do setup of MMU supervisor registers for RAM and I/O space access.
;  Also do read check after write and abort if error.
;--------------------------------------------------------------------------

;  Do origin registers first

SETMMU  MOVE.L  #MMUSADRB,A0    ;GET MMU PTR
        MOVEQ   #0,D0	        ;clear for use
        MOVEQ   #0,D1
        MOVE    D2,D4	        ;SAVE PREVIOUS RESULTS IF ANY
        MOVEQ   #0,D2
        MOVEQ   #0,D6
        MOVE.L  #ADR128K,A2     ;ADDRESS INCREMENT
        MOVE.L  #PAG128K,A3     ;SET UP BASE ADDRESS INCREMENT
        MOVEQ   #16,D6	        ;LOOP COUNT
LOADORG BSRS4   CHKRW	        ;DO WRITE/READ CHECK
        ADD.L   A3,D0	        ;COMPUTE NEXT MEMORY BASE ADDRESS
        ADDA.L  A2,A0	        ;BUMP MMU ORG PTR
        SUBQ    #1,D6
        BNE.S   LOADORG	        ;LOOP UNTIL DONE

;  Set base for I/O and special I/O space

        MOVEA.L #MMU126B,A0     ;PT TO ORG REG 126
        MOVEQ   #0,D0	        ;set data value
        BSRS4   CHKRW
        ADDA.L  A2,A0	        ;BUMP PTR TO REG 127
        BSRS4   CHKRW

;  Now do limit registers

        MOVEA.L #MMUSADRL,A0    ;GET MMU LIMIT REG PTR
        MOVE    #MEMLMT,D0      ;LIMIT FOR 128K MEMORY SEGMENTS
        MOVEQ   #0,D1	        ;use as working reg
        MOVEQ   #16,D6	        ;LOOP COUNT
LOADLMT BSRS4   CHKRW
        ADDA.L  A2,A0	        ;BUMP MMU PTR
        SUBQ    #1,D6
        BNE.S   LOADLMT	        ;LOOP UNITL DONE

;  Now do MMU limit reg setup for I/O and Special I/O access

        MOVEA.L #MMU126L,A0     ;PT TO LMT REG 126
        MOVE    #IOLMT,D0       ;SET FOR I/O SPACE, FULL ACCESS
        BSRS4   CHKRW
        ADDA.L  A2,A0	        ;BUMP PTR TO REG 127
        MOVE    #SPLMT,D0       ;SET FOR SPECIAL I/O, FULL ACCESS
        BSRS4   CHKRW

        .IF  DIAGS = 1
;  Check if errors detected

        TST     D2	        ;CHECK ERROR MASK
        BNE     MMUERR	        ;ABORT IF ERROR
        MOVE    D4,D2	        ;ELSE RESTORE PREVIOUS RESULTS
        .ENDC

        .PAGE
;--------------------------------------------------------------------------
;  Complete testing of MMU by checking other context regs.
;  Uses reg D6 for context indicator.
;--------------------------------------------------------------------------
        .IF     DIAGS = 1

MMUTST2 MOVEQ   #0,D6	        ;FOR CONTEXT INDICATOR
        BSR4    MMUINIT	        ;REINITIALIZE FOR TESTING

        TST.B   SEG1ON	        ;SET FOR CONTEXT 1
        MOVEQ   #1,D6	        ;SET CONTEXT INDICATOR

        BSR4    CONCHK	        ;CHECK IF MMU CONTEXT CHANGED
        BEQ     MMUERR2	        ;EXIT IF NO - SEG BIT ERROR

        BSR6    MMURW	        ;ELSE GO DO R/W TEST
        BNE     MMUERR2	        ;exit if error

        TST.B   SEG2ON	        ;SET FOR CONTEXT 3
        MOVEQ   #3,D6

        BSR4    CONCHK	        ;CHECK IF MMU CONTEXT CHANGED
        BEQ.S   MMUERR2	        ;EXIT IF NO - SEG BIT ERROR

        BSR6    MMURW	        ;ELSE GO TEST
        BNE.S   MMUERR2	        ;exit if error

        TST.B   SEG1OFF	        ;SET FOR CONTEXT 2
        MOVEQ   #2,D6

        BSRS4   CONCHK	        ;CHECK IF MMU CONTEXT CHANGED
        BEQ.S   MMUERR3	        ;EXIT IF NO - SEG BIT ERROR

        BSRS6   MMURW	        ;ELSE GO TEST
        BNE.S   MMUERR3	        ;exit if error

        TST.B   SEG2OFF	        ;RESET FOR CONTEXT 0 REGS

;  Now do MMU addressing check of remaining context regs

        BSR4    MMUINIT	        ;REINITIALIZE

        TST.B   SEG1ON	        ;SET FOR CONTEXT 1
        MOVEQ   #1,D6
        BSR6    MMUACHK	        ;TEST CONTEXT 1
        BNE.S   MMUERR2	        ;exit if error

        TST.B   SEG2ON	        ;TEST CONTEXT 3
        MOVEQ   #3,D6
        BSR6    MMUACHK
        BNE.S   MMUERR2	        ;exit if error

        TST.B   SEG1OFF	        ;TEST CONTEXT 2
        MOVEQ   #2,D6
        BSR6    MMUACHK
        BNE.S   MMUERR3	        ;exit if error

        TST.B   SEG2OFF	        ;RESET TO CONTEXT 0
        BRA.S   MMULPCHK        ;go check for loop mode

MMUERR2 TST.B   SEG1OFF	        ;ENSURE RESET FOR CONTEXT 0
MMUERR3 TST.B   SEG2OFF

        ROR …

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