LISA Hardware REFERENCE MANUAL Bill Schottstaedt Ext. 2379 Conf i,den tial Lisa Hardware Reference Manual TABLE OF CONTENTS OVERVIEW 4 5 5 6 The Processor Video Display Memory The System Bus THE CPU BOARD 7 7 9 9 10 12 12 13 14 15 16 17 18 18 20 21 23 24 25 The 68000 Interrupts Memory Memory Configurations The Memory Management Unit The Segment Origin Context Selection The Segment Limit The Process Stack Loading·the MMU Registers Memory Errors The Status Register The Memory Error Address Latch Memory Diagnostic Mode Video Circuit Contrast Control System Bus Timing Memory Bus Timing Summary of MMU Locations THE 10 BOARD 26 26 28 31 32 32 34 34 35 36 37 38 39 40 42 42 44 44 45 The Input/Output Board The Keyboard Interface COPS Command Timing Reset Codes The Keyboard Keycodes The Mouse Mouse Commands Mouse Data The Clock/Calendar Circuit Setting the Clock The CVSD and the Speaker The Serial Interface Baud Rate Generation The Floppy Disk Controller Disk Controller Commands Disk Data Storage Interrupts Non-volatile Memory 7-Jul-81 Confidential 45 Lisa Hardware Reference Manual The Battery The Hard Disk Interface I/O Space Addresses 46 51 THE EXPANSION I/O SLOTS 53 53 57 58 The Expansion I/O Slots Signal Description Device Protocol Direct Memory Access GLOSSARY SCHEMATICS ,7-Jul-81 Lisa Hardware Reference Manual Confidential 7-Jul-81 HARDWARE OVERVIEW The Lisa hardware can be divided into four functional pieces: the CPU and memory management unit, the I/O circuitry, the memory arrays, and the expansion slots. The main microprocessor is a Motorola MC68000. It communicates with the rest of the Lisa world over two buses: the system bus, and the memory bus. The I/O circuitry includes the built-in parallel interface, two serial interfaces, floppy disk controller, clock-calendar, speaker, and keyboard interface. SYSTEM BLOCK DIAGR&~ ------- ---+ Expansion Slot a I +--_._-,-----+ +---------- +-----------+ -I I Memory Array 1 I I Expansion Slot 1 I +--------+ +------------+ +------ +-----------i- I -=+ I Expansion Slot 2 Memory Array 2 I -- ... _------+ System Bus --------------.._--_.._--------------+ .--+ -+--I/O BOARD: Floppy Disk Controller Hard Disk Interface Keyboard Interface Speaker and CVSD Serial I/O Ports Clock/Calendar/Alarm +------ I I I I I I I I +--------- ---_._---- . - + I I I I' I I I ----+ Memory Bus CPU BOARD: 1 I ( 68000 and Buffers Memory Management Unit I Boot and diagnostics ROM I Video Circuitry I Memory Access Control I I , I +-------------...=-----+ THE PROCESSOR The Motorola MC68000 Microprocessor User's Manual fully describes the operation of the processor, including its instruction set and timing. The Lisa 68000 has a 5 megahertz clock. The memory cycle time is 800 nanoseconds; therefore instructions that use a multiple of four clock cycles can execute without a wait state. Page 4 Lisa Hardware Reference Manual Confidential 7-Jul-81 VIDEO DISPLAY The bit mapped d…

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September 7th 1982 LISA Hardware Manual LISA HARDWARE MANUAL Forrest Warthman and Associates Final Draft September 7th 1982 Author: D. Berry September 7th 1982 LISA Hardware Manual PREFACE (Full Version Only) The LISA Hardware Manual is concerned with the internal functioning of the LISA system. It is intended for use by people concerned with the detailed functional operation of the LISA hardware. It is divided into two sections. Section I provides information on the functional performance and specification of the system. Chapter 1 provides a general introduction to the Lisa system, while giving a brief description of the system architecture. Chapter 2 will be of interest to programmers who need to know the address and interrupt structure, as well as the operation of the Memory Mapping Unit. Chapter 3 contains in!ormation on dimensions and environmental requirements and interfaces to the system, which are of use to design engineers wishing to interface to the Lisa. Section II of the· manual contains full functional. descriptions and theory of operation for each of the modules in the Lisa system. It will not be of interest to the general reader and is intended for use only by design and service personnel. Section II includes chapters on: * * * * * * * * The _processor board The memory board The I/O board The video board The operator interface The floppy disk unit The power supply System assembly The appendices supply schematics for the system components. Other documents relevant to the system are: * * * * LISA Hardware Manual (Condensed Version) LISA Floppy Disk Drive Manual LISA Owner's Guide LISA Operating System Manual * * * * * * Motorola 68000 User's Manual Motorola 6504 User's Manual Motorola 6522 Data Sheet COPS42l User's Manual 8530 sec User's Manual AMD 9512 Data Sheet xii LISA Hardware Manual September 7th 1982 TABLE OF CONTENTS Preface -- Section I -- Chapter 1 1.1 1.2 1.3 1.4 1.S 1.6 1.7 1.8 Chapter 2 SYSTEM ARCHITECTURE System Layout • • • • • • • • • • 1-1 Hardware Structure • • • • • • • • • • 1-4 The Central Processing Unit • • • • • • 1-6 f-temory • • '. • • • • • • • • • 1-6 Internal Buses • • • • • • •• •• 1-10 Storage Media • • • • • • • • • • • • • 1~11 User In'terfaces • • • • • • • • • • • • .1-11 Additional Features • • • • • • • • 1-11 SYSTEt-t PROGRAUMING 2.3 ..·.·.. 2-1 CPU Registers and Their Osp. · . . • .•.• 2-2 Memory Management Scheme 2-3 · · ·· •• ·· ·· •· 2-5 2.3.1 Address Transformation 2.3.2 The MMU Registers • 2-8 · · · · · · 2.3.3 MMU Initialization 2-11 2.3.4 System Contexts • · · · · · · · • ·• ·• 2-13 2.4 Addressing in Special I/O Space • • • • 2-15 2.5 System I/O Map. '. • • • • • 2-15 2.5.1 Floppy Disk Control • 2-16 • • • 2.5.2 Serial Port Control • 2-19 • • 2.5.3 Parallel Port Control • 2-22 • 2.5.4 Keyboard/Mouse Control 2-26 2.5.5 Processor Board Control • • 2-33 2.6 Interrupt Handling 2.7 Error Processing 2.8 System Status • • • 2.1 2.2 The Instruction Set ii . …

F~l Version 2.0 July 14" 1983 Please direct your COlITIEnts in fII.l"iting to: Gary ttarten I1S 2R Peul 88ker IfS 2R Ann Nunziata ItS 2R I Apple Computer Confidential ApprovalS Engineering SOftware Engineering ,fvlaIkeUn:1 < Marufacturtng .~. Mass Star. Dtvision Approval of ."..~ Whopper" project by the ·aoove releases "The Wl1Opper" as defined by this doCu'nent. All' fUture Changes, If Sly, fTlJStbe agreed ~ by above. lheCtJ~t ' , , The Lls~ haS evolvedto be a falrly COfllllexCitd expensive system to build. OUr initial idea of 'Ntlat the hardWc31e would be has grown sl~lflcantly dUe to software requlrements.and f1aS grealtly increased the cost of.the.Lisa system to ~le ana the customer.' " The LIsa system has iune:rous tlOarC2s in it. The bOardS/SUbSyStems 1rolUC1eO 1n tne Llsa assencly are : ~ o 1-QlU . 0 1- 11.0 .. . 0 2 - 1/2 tEl t1eIoory cards o l~' Power Sl4lPly o 1- Video . .' o 2 - floppy D1Sk Dr1ves . o 1 - Profile Hard 1~1Sk aSS8ftt)ly .. The goal of the, IIIhopper 1~» to repackage the aboVe tlard~e 1n the exi sting Lisa package 1n sucn a way that the packag~no CleSigl 1s m1n~m1zea .n1le the sate functionality 1s prov1dEtd to·tne user for lower cost. In specific, tt:e care cage, power supply, v1t1EKt board, CI1dtne DiSk assetlOl1es .aula De cnangea while Rt.tCh of the package and the keyobard wouldrema1n the sane. The Lisa card cage contains four plug-tn caras; tne wnopper logic will De conta1nea on two ,.cards. In addition a hard diSk cantle 1nstall891n place of cne of the floppy dr1ves, tnus eliminating toe cost Of one floppy and tneProf11e packag1ng <nl power s u p p l y . ' . The final Whopper System ~ld trus have the following conf1gurat1oo: o'lCHiZ 68010 prt':a~ssor 0' Mt1U w1 ttl 512 byte pages crtd 4, t'8 teal address space , < . o 720 x 544 videO (w1 ttl 720 x 364 RJlde) , o 1281< Ra1 (max1f1U1'J) o 896K RAM (max1nunl withOUt expans10n card) o Bu1lt-in SOny Floppy DiSk drive ' o Bull t-in Widget Hard DiSk dr1ve o 2 Bu1l t -in serial ports o Keyboard/f1OJS8 1"terface .,1th TOO clOCk To emance the COItfJ8t1b111ty bet.een ~r f.nj Mac, a"square dOts" videO rooae1s prov1ded, the SOny Floppy Disk'dr1ve 1s used and a "Mac-like SCUl(j" generator 1s provided. ca,s1derable software effort w1ll still be required to make Hac applications 1\1"\ (lI'l the M1tRlef. In addition to tne electrical des1!J1 the M1tRler ,,111 requ1re mechanical Clesl~ to prev1ae new sneet Etal for IIO.I1ting the d1sk drives ana a1 fferent card cage ~ts. Anew power cable namess w111 also haVe to be desit7l8d. COst rec:lJCtion 1s a'l1~!1:ant part Of tile WlOpperproJect ana these parts w111 be redeSigned in the nest Ctlst ~ffect1ve IIS'V'lef poss1ble. ~ly 14, 1983 - 1- The _hopper ERS . D1ffeI'8ceslntte~ , " , from A s1gn1,f1cant space rectuctlon 1n the '~r' C(JES theflCtRly diSk cootroller, which 1n the lisa I1s abOUt. 30 IC' s anct ~ies abOUt 1/2 the lID board. This 1s r~ to the s1ngle XWi Chipancfseveral 1/0 b1ts 1n…

--·--- Lisa 1 .75 ROM --------·----------------------·----------------..,-------------~-- To: From: Date: Subject: Ron Johnston, Marian Catelain, Ken c.<in, Gary Marten Rick ·Meyers May 26, 1983 Lisa 1.75 ROM Organization The Lisa· l.75 is expected ti0 have 128K bytes of ROM and 128K bytes of RAfvl on the CPU board. Additional RA!'-1 will range from none·(in a servant) to 768K (full memory board) and upward (given extra memory bo'ards). In a 512K system (assuming a 512K memory board, 128K CPU F~OM, 128K CPL,J RAM), the CPU ROM and RAM account for one third of the memory in the entire system. It's extremely important that we use this CPU memory wisely. Careful coordination bet"veen POS hardware and software group will be required. This memo outlines some of the planning that snould begin 1mmec:Uate1y. 1'1ernory COntents and Budgf!ts we need to carefully select both ROM· ancJ RAf'-1 contents, and budget their use of memory. Possible ROM .contents include: · • diagnostics (CPU, memory, peripherals) • boot code (ini tiallzation, load from disk) . • hardware interface (cursoJ, mouse, keyboards, s·peaker, timers, clock, power, etc.) • drivers (built in disk, twiggy, profHe, priam, RS-232, printers) ,. • partial file system· (for booting, keyboard tables, preferences, etc.) • miniature dubugger • fonts · • QuickDraw Possible RAl'-1 contents include: ., • primary screen (32,...() • optional al temate s;creen (32K) • interrupt and trap vectors (defaults, soft vectors, etc.) 0 hardware interface global data (keyboard mapping, keyboard queue, timers, etc.) • QulcKDraw. global o~ata (screen size, address, etc.) · • disk buffers, caches: ' . ·. • debugger data area (regis,ters, oreakpolnts, etc.) Ard'li tecture The dependencies between tlhe possible ROM contents are complex. For example: • diagnostics need hardware interface, fonts, QuickDraw • boot code needs halrdware interfac:e, drivers, file system • hardware Interface needs dr,lvers and me system (for keyboard definitions) • debugger needs nardware interface, but· hardware. interface must oe. deougged • QuickDraw needs hardware interface • etc. ·· 'There is no currently no linear ordering of the ROM software components which expresses the dependencies. This mak~s ~ layered organizatiori difficult Unfortunately, some ordering is require1ci, if only for initialization. we ~eed to break free from our current organization (or lack thereofl,. shuffle the software around, and define easily understood relatlonsnlps between the ROM components. Ga.llirg Cooventloos Calling conventions must. satisfy assembly language, Pascal, etc. How do we get Pascal lil~raries (QuickOraw, HW!nt, etc.) to point to ROM? If a ROM routine needs to be replaced, now do we override it in RA1'1? Certain ROM routines. will need domain and/or privlledged mode. Mechanism? Bad addresses as parameters to the ROM wm cause disaster. How is this preventea? 1 a Default interrupt and ~p han~lers will be In ROM. How .are t…