;===================================================================================
;
; File:		ApplPrimaryInit.a
;
; Entry:	VendorPI
;
; Function:	Zorro initialization code 
;   {
;	for (count = loopcount; ((count >0) && (bcpTestState != DONE)); count--)  {};
;	if ((bcpTestState != DONE) || (bcpTestErr))
;	   error();
;	stop_bcp();
;	Test 8344 Data RAM locations 0x0000-0x3FFF with patterns FF, AA, 55, and 00;
;	Test 8344 address lines;
;   }
;
; Input:	D0 = Current current test state 
;		A2 = slot address
;		A3 = ptr to Slot Manager parameter block
;
; Output:	D1 = PASS or FAIL
;		($138) = 32 bit failure code if D1 == FAIL
;
; Update:	D0, A2, A3 preserved
;
; History:	12/03/87: initial version
;
;===================================================================================

	EJECT
;bcpRIC		equ	$420001			; 8344 remote interface configuration register
;bcpPC		equ	$400001			; Dummy address for writing to 8344 PC
;bcpDRAM		equ	$400001			; 8344 Data RAM address base
;bcpDMEnd	equ	$4000 * 2 + bcpDRAM	; Last data memory + 1
;RIC_DRAM	equ	$30			; Select 8344 Data RAM
;PASS		equ	0
;FAIL		equ	-1
		
VendorPI: 
	move.l	D0, -(sp)		; save test state
	move.l	A2, -(sp)		; save slot address
	move.l	A3, -(sp)		; save Slot Mgr Parameter block ptr
	move.l	D0, $150(A2)
	move.l	D1, $154(A2)
	move.l	D2, $158(A2)
	move.l	D3, $15C(A2)
	move.l	A0, $160(A2)
	move.l	A1, $164(A2)
	move.l	A2, $168(A2)
	move.l	A3, $16C(A2)
	
;
; - Test 8344 Data RAM
;

	movea.l	#bcpDRAM, A4		; point to location 0000 of data memory
	adda.l	A2, A4			; add slot address
	movea.l	#bcpDMEnd, A3		; ending location
	adda.l	A2, A3			; add slot address
	jsr	zi_RAM			; test interface area (0x0000 - 0x3FFF)
	bne.s	zi_err			; skip if error
	move.l	#PASS, D1		; no error
	bra.s	zi_rtn			; exit	

;---------------------------------------
; - Error exit
;---------------------------------------

zi_err:
	move.l	#FAIL, D1		; test failed
	
;---------------------------------------
; - Exit
;---------------------------------------

zi_rtn:
	move.l	D0, $170(A2)
	move.l	D1, $174(A2)
	move.l	D2, $178(A2)
	move.l	D3, $17C(A2)
	move.l	A0, $180(A2)
	move.l	A1, $184(A2)
	move.l	A2, $188(A2)
	move.l	A3, $18C(A2)
	move.l	(sp)+, A3		; restore Slot Mgr Parameter block ptr
	move.l	(sp)+, A2		; restore slot address
	move.l	(sp)+, D0		; restore test state
	move.l	D0, $190(A2)
	move.l	D1, $194(A2)
	move.l	D2, $198(A2)
	move.l	D3, $19C(A2)
	move.l	A0, $1A0(A2)
	move.l	A1, $1A4(A2)
	move.l	A2, $1A8(A2)
	move.l	A3, $1AC(A2)
	
	rts

	EJECT

;===================================================================================
;
; Name:		zi_RAM
;
; Function:	Test 8344 Data Memory 
;
; Input:	A4 = starting RAM address
;		A3 = ending RAM address + 1
;		A2 = slot address
;
; Output:	Z flag set   => no error
;		Z flag clear => error (D1 = data written; D2 = data read back;
;				       A4 = failed address)
;
; Update:	None
;
; History:	12/03/87: initial version
;
;===================================================================================
				
zi_RAM:
	movea.l	#bcpRIC, A1	; address of 8344 RIC
	adda.l	A2, A1		; NuBus address
	move.l	A4, D3		; save starting location
	moveq	#RIC_DRAM, D0	; select Data memory
	move.b	D0, (A1)	;
	move.b	#$FF,D1		; data pattern
@1:
	move.b	D1, (A4)	; write to memory
	cmp.b	(A4), D1	; read it back check
	bne.s	@90		; jump if errror
				
	addq.l	#2, A4		; addr.ptr++
	cmp.l	A3, A4		; check if reached end
	bne.s	@1
				
	movea.l	D3, A4		; reset pointer to where it started
	moveq	#$55,D1		; data pattern
@2:
	move.b	D1, (A4)	; write to memory
	cmp.b	(A4), D1	; read it back check
	bne.s	@90		; jump if errror
				
	addq.l	#2, A4		; addr.ptr++
	cmp.l	A3, A4		; check if reached end
	bne.s	@2
					
	movea.l	D3, A4		; reset pointer to where it started
	move.b	#$AA,D1		; data pattern
@3:
	move.b	D1, (A4)	; write to memory
	cmp.b	(A4), D1	; read it back check
	bne.s	@90		; jump if errror
				
	addq.l	#2, A4		; addr.ptr++
	cmp.l	A3, A4		; check if reached end
	bne.s	@3
				
	movea.l	D3, A4		; reset pointer to where it started
	moveq	#$00,D1		; data pattern
@4:
	move.b	D1, (A4)	; write to memory
	cmp.b	(A4), D1	; read it back check
	bne.s	@90		; jump if errror
				
	addq.l	#2, A4		; addr.ptr++
	cmp.l	A3, A4		; check if reached end
	bne.s	@4
	
	rts			; good return
@90:
	move.b	(A4), D2	; D2 = data read back
	move.b	#1, D3		; insure Z = 0
	rts			; return
	
	
;===================================================================================
; Entry:	(Status indicator routines)
;
; Function:	
;	When execution of primary init begins, ShowInProgress (which could turn on all LEDs)
;	is called, indicating that the test is in progress.  if primary init crashes
;	it will then be evident that testing did not complete.  If any tests fail,
;	the routine ShowFail is called (perhaps to leave on a red LED), and if all 
;	self-tests pass, the routine ShowPass is called (perhaps to leave on a red LED). 
;	ShowOff is called to turn off all indicator status.
;   
; 	Remember that the following routines are executed across NuBus, and therefore
;	32 bit NuBus addressing must be used.
;===================================================================================

ShowInProgress:			;turn on red & green LED or do whatever to indicate test running
				;Reg A2 contains the 32 bit base address of the card
	move.l	d1, -(sp)	;save & restore any registers changed
	move.l	#$600001, d1	;currently defined Zorro LED control register
	move.b	#$3, (a2, d1.l) ;write to LED control register (turn on red & green)
	move.l	(sp)+, d1
	rts			
	
ShowPass:			;turn on green LED or do whatever to indicate good status
				;Reg A2 contains the 32 bit base address of the card
	move.l	d1, -(sp)	;save & restore any registers changed
	move.l	#$600001, d1	;currently defined Zorro LED control register
	move.b	#$1, (a2, d1.l) ;write to LED control register (turn on green only)
	move.l	(sp)+, d1
	rts			
	
ShowFail:			;turn on red LED
				;Reg A2 contains the 32 bit base address of the card
	move.l	d1, -(sp)	;save & restore any registers changed
	move.l	#$600001, d1	;currently defined Zorro LED control register
	move.b	#$2, (a2, d1.l) ;write to LED control register (turn on red only)
	move.l	(sp)+, d1
	rts			
	
ShowOff:			;turn off green & red LED
				;Reg A2 contains the 32 bit base address of the card
	move.l	d1, -(sp)	;save & restore any registers changed
	move.l	#$600001, d1	;currently defined Zorro LED control register
	move.b	#$0, (a2, d1.l) ;write to LED control register (turn off green & red)
	move.l	(sp)+, d1
	rts			
	
	EJECT

;-------------------------------------------------------------------
;
; (c) Apple Computer, Inc.	1987
; All rights reserved.
;
;-------------------------------------------------------------------
;
;	File   	: CommROM.a
;	Author 	: Michael Klassen, June 8, 1987.
;	Description : This file contains the data structure definition 
;		    for the MCP Comm Engine card.
;
;-------------------------------------------------------------------
;	Modification History :
;
;	7 March 1988: WHJW:  mods to support multiple ROM vers w/ same source code
;	8 July  1988: WHJW:	 Correctly identified slot resource list entries
;-------------------------------------------------------------------

;*************************************************************
;Constants
;*************************************************************
  
	INCLUDE	'CommDeclr.h'  
	INCLUDE	'Application.h'  
	
	
	
;Include files
	PRINT	OFF
	INCLUDE	'DeclROMEqu.a'	;Declaration ROM EQU's
	INCLUDE	'SlotMgrEqu.a'	;Slot Manager EQU's
	PRINT	ON


CommROM	MAIN
	STRING 	C
				

;===============================================================================
; Power-On test
; The following jsr PowerOn must be the first instruction of code in the ROM.
; PowerOn tests RAM, ROM, & will then call the Vendor Powerup test defined in ApplPoweron.a
;===============================================================================

	IMPORT	PowerOn		;from powerup.a
	
	jsr	PowerOn

;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;		Resource	Directory 
;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;							<ID>	<OFFSET/DATA>	
_sRsrcDir	OSLstEntry  	sRsrc_Board,_sRsrc_Board	;<sRsrc_Board>  <Board sRsrc List offset>
	OSLstEntry	sRsrc_CPU, _sRsrc_CPU 	; defines CPU, MCP architecture
	OSLstEntry	sRsrc_Comm1, _sRsrc_Comm1	;category Communications
	OSLstEntry	sRsrc_Comm2, _sRsrc_Comm2	;category Communications
	OSLstEntry	sRsrc_Comm3, _sRsrc_Comm3	;category Communications
	OSLstEntry	sRsrc_Comm4, _sRsrc_Comm4	;category Communications
	DatLstEntry	EndOfList,0		;<EndOfList>    <0>



;=============================================================
;			sRsrc_Board List
;=============================================================
;						<ID>		<OFFSET/DATA>	
_sRsrc_Board OSLstEntry	sRsrc_Type,_BoardType	;<sRsrc_Type>  <Board Type offset>
	OSLstEntry	sRsrc_Name,_BoardName	;<sRsrc_Name>  <Name of Board offset>
	DatLstEntry	BoardId,CommBoardId		;<BoardId>     <CommBoardId>
	OSLstEntry	PrimaryInit,_sPInitRec	;<PrimaryInit> <_sPInitRec record offset>
	OSLstEntry	VendorInfo,_VendorInfo	;<VendorInfo>  <_VendorInfo record offset>
	DatLstEntry	EndOfList,0		;<EndOfList>    <0>

_BoardType 	DC.W	CatBoard			;Board sResource :	<Category>
		DC.W	TypBoard			;<Type>		
		DC.W	0			;<DrvrSw>	
		DC.W	0			;<DrvrHw>	
_BoardName	DC.L	'Apple 3270/5250 NB'	;Official Name of Board
				
;-------------------------------------------------------------
;			Vendor Info record
;-------------------------------------------------------------
_VendorInfo	OSLstEntry	VendorId,_VendorId	;<VendorId>  <VendorId offset>
		OSLstEntry	RevLevel,_RevLevel	;<RevLevel>  <RevLevel offset>
		OSLstEntry	PartNum,_PartNum	;<PartNum>   <PartNum offset>
		DatLstEntry	EndOfList,0	;<EndOfList>  <0>

_VendorId		DC.L	'Copyright (C) 1988 Apple Computer'	;Vendor Id
_RevLevel		DC.L	'ROM rev. A'		;Revision Level(note new part #)
_PartNum		DC.L	'342-0667 (H) 342-0666 (L)'	;Part Number


;=============================================================
;			sRsrc_CPU List
;=============================================================
;						<ID>		<OFFSET/DATA>	
_sRsrc_CPU OSLstEntry	sRsrc_Type,_CPUType		;<sRsrc_Type>  <Board Type offset>
	OSLstEntry	sRsrc_Name,_CPUName		;<sRsrc_Name>  <Name of Board offset>
;	OSLstEntry	sRsrc_DrvrDir,_ComDrvrDir	;<sRsrc_DrvrDir><Offset to the Driver directory for Comm sResource>
	OSLstEntry  	MinorBaseOS, _MinorBase
	OSLstEntry  	MinorLength, _MinorLength
	OSLstEntry	sRsrc_sMemory, _sRsrc_sMemory	; defines card memory mapping
	DatLstEntry	EndOfList,0		;<EndOfList>    <0>

_CPUType 		DC.W	CatCPU			;Board sResource :	<Category>
		DC.W	Typ68000			;<Type>		
		DC.W	DrSwNotThere		;<DrvrSw>	
		DC.W	DrHwAMCP			;<DrvrHw>	
_CPUName		DC.L	'CPU_68000_none_AppleMCP'	;Name of CPU
				
_MinorBase	DC.L	0			;Offset is 0
_MinorLength	DC.L	$1000000			;memory map length is 16 Meg

;=============================================================
;			_sRsrc_sMemory List
;=============================================================
;						<ID>		<OFFSET/DATA>	
_sRsrc_sMemory OSLstEntry	sRsrc_Type,_sMemoryType	;<sRsrc_Type>  <Board Type offset>
	OSLstEntry	sRsrc_Name,_sMemoryName	;<sRsrc_Name>  <Name of Board offset>
	OSLstEntry  	MinorRAMAddr, _MinorRAMAddr
	OSLstEntry  	MinorROMAddr, _MinorROMAddr
	OSLstEntry  	MinorDeviceAddr, _MinorDeviceAddr
	DatLstEntry	EndOfList,0		;<EndOfList>    <0>

_sMemoryType 	DC.W	CatsMemory		;Board sResource :	<Category>
		DC.W	1			;<Type>	MCP type	
		DC.W	DrSwNotThere		;<DrvrSw>	
		DC.W	DrHwAMCP			;<DrvrHw>	
_sMemoryName	DC.L	'sMemory'			;Name of resource

_MinorRAMAddr 	DC.L	12			;block size in bytes
		DC.L	$400000			;RAM length (Architecture allows up to 4 Meg)
		DC.L	$0			;RAM base offset

_MinorROMAddr 	DC.L	12			;block size in bytes
		DC.L	$10000			;ROM length (Architecture allows 64K)
		DC.L	$FF0000			;ROM base offset

_MinorDeviceAddr 	DC.L	_EndMinorDeviceAddr - _MinorDeviceAddr	; Block size
		DC.L	$400000			;no decode/DTACK I/O interface logic length
		DC.L	$400000			;no decode/DTACK I/O interface logic offset
		DC.L	$200000			;decode/DTACK I/O interface logic length
		DC.L	$800000			;decode/DTACK I/O interface logic offset
		DC.L	$200000			;NuBus control range length
		DC.L	$A00000			;NuBus control range offset
		DC.L	$00000b			;MCP control range length
		DC.L	$C00000			;MCP control range offset
_EndMinorDeviceAddr	EQU	*			; End of block

;-------------------------------------------------------------
;				Driver directory (not used)
;-------------------------------------------------------------
;_ComDrvrDir	OSLstEntry	sMacOS68020,_sMacOS68020	;<sMacOS68020>  <sMacOS68020 offset>
;		DatLstEntry	EndOfList,0		;<EndOfList>  	<0>


;Driver-1 (68020).
;_sMacOS68020	DC.L	_End020Drvr-_sMacOS68020	;Physical Block Size
;		INCLUDE	'ComDrvr.a'		;The Header/Code
;_End020Drvr	EQU		*
		STRING 	C
				

;=============================================================
;			sRsrc_Comm1 List
;=============================================================
;			<ID>		<OFFSET/DATA>	
_sRsrc_Comm1 OSLstEntry 	sRsrc_Type,_CommunicationType1	;<sRsrc_Type>  <Network Type offset>
	OSLstEntry	sRsrc_Name,_CommunicationName1	;<sRsrc_Name>  <Name of Network offset>
	DatLstEntry	sRsrc_HWDevId,1			;hardware device ID
	DatLstEntry	EndOfList,0			;<EndOfList>    <0>

_CommunicationType1 	DC.W	CatCommunication	;Board sResource :	<Category>
		DC.W	Typ3270			;<Type>		
		DC.W	DrSwNotThere		;<DrvrSw>	
		DC.W	DrHwAMCP			;<DrvrHw>	
_CommunicationName1	DC.L	'Communication_3270_none_AppleMCP' 	;Name of resource
;=============================================================
;			sRsrc_Comm2 List
;=============================================================
;			<ID>		<OFFSET/DATA>	
_sRsrc_Comm2 OSLstEntry 	sRsrc_Type,_CommunicationType2	;<sRsrc_Type>  <Network Type offset>
	OSLstEntry	sRsrc_Name,_CommunicationName2	;<sRsrc_Name>  <Name of Network offset>
	DatLstEntry	sRsrc_HWDevId,2			;hardware device ID
	DatLstEntry	EndOfList,0			;<EndOfList>    <0>

_CommunicationType2 	DC.W	CatCommunication	;Board sResource :	<Category>
		DC.W	Typ3270			;<Type>		
		DC.W	DrSwNotThere		;<DrvrSw>	
		DC.W	DrHwA3270_5250		;<DrvrHw>, implies 8344 chip
_CommunicationName2	DC.L	'Communication_3270_none_8344' 	;Name of resource
;=============================================================
;			sRsrc_Comm3 List
;=============================================================
;			<ID>		<OFFSET/DATA>	
_sRsrc_Comm3 OSLstEntry 	sRsrc_Type,_CommunicationType3	;<sRsrc_Type>  <Network Type offset>
	OSLstEntry	sRsrc_Name,_CommunicationName3	;<sRsrc_Name>  <Name of Network offset>
	DatLstEntry	sRsrc_HWDevId,3		;hardware device ID
	DatLstEntry	EndOfList,0		;<EndOfList>    <0>

_CommunicationType3 	DC.W	CatCommunication	;Board sResource :	<Category>
		DC.W	Typ5250			;<Type>		
		DC.W	DrSwNotThere		;<DrvrSw>	
		DC.W	DrHwAMCP			;<DrvrHw>	
_CommunicationName3	DC.L	'Communication_5250_none_AppleMCP' 	;Name of resource

;=============================================================
;			sRsrc_Comm4 List
;=============================================================
;			<ID>		<OFFSET/DATA>	
_sRsrc_Comm4 OSLstEntry 	sRsrc_Type,_CommunicationType4	;<sRsrc_Type>  <Network Type offset>
	OSLstEntry	sRsrc_Name,_CommunicationName4	;<sRsrc_Name>  <Name of Network offset>
	DatLstEntry	sRsrc_HWDevId,4		;hardware device ID
	DatLstEntry	EndOfList,0		;<EndOfList>    <0>

_CommunicationType4 	DC.W	CatCommunication	;Board sResource :	<Category>
		DC.W	Typ5250			;<Type>	5250	
		DC.W	DrSwNotThere		;<DrvrSw>	
		DC.W	DrHwA3270_5250		;<DrvrHw>, implies 8344 chip
_CommunicationName4	DC.L	'Communication_5250_none_8344' 	;Name of resource


; DO NOT ADD ANYTHING BELOW THIS LINE OR THE PRIMARY INIT CODE WILL FAIL!!!


;-------------------------------------------------------------
;			Primary Init Record
;-------------------------------------------------------------
_sPInitRec	DC.L	_EndsPInitRec-_sPInitRec	;Physical Block Size
		INCLUDE	'PrimaryInit.a'		;The Primary Init Header/Code
_EndsPInitRec	EQU		*		;End of block
		STRING 	C

	DC.W	VendID			; unofficial 3270/5250 id
	DC.W	CommID			; unofficial MCP architecture id
;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;			Format/Header Block
;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
	DC.L	(_sRsrcDir-*)**$00FFFFFF	;Offset to sResource directory
	DC.L	ROMSize			;Length of declaration data
	DC.L	0			;CRC {Patched by crcPatch}
	DC.B	ROMRevLevel		;ROM Revision level defined in application.h
	DC.B	AppleFormat		;Format
	DC.L	TestPattern		;Test pattern
	DC.B	0			;Reserved byte
	DC.B	$0F			;ByteLanes: 0000 1111

	ENDP
	END

MC68020 Assembler - Ver 2.88                                                                               14-Dec-88  Page   1
Copyright Apple Computer, Inc. 1984-1987

Loc   F Object Code     Addr  M	Source Statement


                               	;-------------------------------------------------------------------
                               	;
                               	; (c) Apple Computer, Inc.	1987
                               	; All rights reserved.
                               	;
                               	;-------------------------------------------------------------------
                               	;
                               	;	File   	: CommROM.a
                               	;	Author 	: Michael Klassen, June 8, 1987.
                               	;	Description : This file contains the data structure definition
                               	;		    for the MCP Comm Engine card.
                               	;
                               	;-------------------------------------------------------------------
                               	;	Modification History :
                               	;
                               	;	7 March 1988: WHJW:  mods to support multiple ROM vers w/ same source code
                               	;	8 July  1988: WHJW:	 Correctly identified slot resource list entries
                               	;-------------------------------------------------------------------

                               	;*************************************************************
                               	;Constants
                               	;*************************************************************

                               		INCLUDE	'CommDeclr.h'
                               	;*************************************************************************
                               	;
                               	; CommDeclr.h:
                               	;	Constants used for Smart card Diagnostics

        0007 FFFE              	STACK			EQU	$7FFFE		; offset of stack in card RAM
        0001 0000              	ROMSize			EQU	(64*1024)	; ROM = 64K

        0000 0000              	OFF				equ	0
        FFFF FFFF              	ON				equ	-1
        0000 0000              	PASS			equ	0
        FFFF FFFF              	FAIL			equ	-1
        0000 0001              	WAIT			equ 1

                               	; Delay constants in microseconds
        0000 0D00              	TimeDBRA		equ $D00		; (word) location: # of DBRA instructions/mSecond
        0000 01F4              	WaitCount		equ	500			; timeout  - wait for power_on finish
        0000 0004              	TimeCnt			equ	4			; timeout for IOP test
        0000 0010              	TimerWait 		equ	16			; timeout for Timer test
        0000 0004              	Delay			equ	4			; Reset delay

                               	; variable offsets into card RAM
        0000 0100              	WaitFlag		equ	$100		; power_on wait flag
        0000 0102              	TstStatus		equ	$102		; test status bit flags
        0000 0104              	TimeFlag		equ	$104		; flag for timer test
        0000 0106              	HostFlag		equ	$106		; flag for host reset test
        0000 0108              	ResetFlag		equ	$108		; flag to control reset code
        0000 010C              	IOPFlag			equ	$10C		; flag for IOP interrupt test
        0000 010E              	CRCCalcAddr 	equ	$10E		; ROM calculated CRC value
        0000 0112              	WriteLoc		equ	$112		; Location of Nubus write/read test
                               	;rteAddr			equ	$116	; rte for interrupt vectors (no longer used)
        0000 0118              	timeCountAddr 	equ	$118		; address of firmware timer counter
        0000 011C              	RAMSizeAddr		equ $11c		; Size of card RAM in bytes
        0000 0120              	TASStatusAddr	equ $120		; returns test & set card status to 020
        0000 0122              	NMRQFlag		equ	$122		; flag for NMRQ test
        0000 0128              	BusErrAddr		equ	$128		; flag for bus error
        0000 012C              	InitA5Addr		equ $12c		; Used for finding data block
        0000 0130              	CodeOffset		equ $130		; Used for finding code block
        0000 0134              	VendPowerStatus	equ $134		; return status from vendors power-up code
        0000 0138              	VendPrimaryStatus equ $138		; return status from vendors Primary init code
        0000 013C              	ExceptionPC		equ $13C		; PC stored here after exception takes place
        0000 0140              	ErrorAddr		equ $140		; data addr stored here after bus or addressing error
        0000 0144              	RAMErrAddr		equ	$144		; if RAM error occurs, its address stored here
        0000 0148              	L1IntAddr		equ	$148		; Mac processor stores new Timer interrupt loc here;
                               									; then calls SetL1Interrupt to set it safely.
                               	; card space to $180 to $200 reserved for temporary data values only
        00E0 0000              	testROMAddr   	equ	$e00000		; location of Fremont board tester ROM
        0080 0008              	ROMversion		equ $800008		; location of Mac II ROM version number

                               	; Test status bit masks

MC68020 Assembler - Ver 2.88                                                                               14-Dec-88  Page   2
Copyright Apple Computer, Inc. 1984-1987

Loc   F Object Code     Addr  M	Source Statement

        0000 FFFF              	testsDefined 	equ	$ffff		; currently defined test bits
        0000 FFFE              	DLTestMask		equ	$fffe		; sliding 5  data line test
        0000 FFFD              	RAMTestMask		equ	$fffd
        0000 FFFB              	testPatternMask equ	$fffb		; signals PROM burned incorrectly
        0000 FFF7              	CRCTestMask		equ	$fff7		; Clears CRC test bit
        0000 FFEF              	VendPowerupMask equ	$ffef
        0000 001F              	PowerMask		equ	$1F
        FFFF FFDF              	BusMask			equ	$FFFFFFDF	; clears Nubus write/read test bit
        FFFF FFBF              	HostMask		equ	$FFFFFFBF	; clears host reset test bit
        FFFF FF7F              	TimeMask		equ	$FFFFFF7F	; clears timer test bit
        FFFF FEFF              	IOPMask			equ	$FFFFFEFF	; clears IOP test bit
        FFFF FDFF              	VendMask		equ	$FFFFFDFF	; clears vendor test bit
        FFFF FBFF              	NMRQMask		equ $FFFFFBFF	; clears NMRQ test bit

                               	; Card control switch offsets
        00C0 0000              	ExtReg			equ	$C00000		; Nubus extension register (write) or unreset (read)
        00C0 0002              	TimerSet		equ	$C00002		; Timer interrupt switch (read)
        00C0 0008              	ClrIOPIntr 		equ	$C00008		; Clear Interrupt IOP request (read)
        00C0 000A              	SetIOPIntr 		equ	$C0000A		; Set Interrupt IOP request (read)
        00C0 0004              	ClrHostIntr 	equ	$C00004		; Clear Host Interrupt request (read)
        00C0 0006              	SetHostIntr 	equ	$C00006		; Set Host Interrupt request (read)
        00F0 0000              	Reset			equ	$F00000		; programmed reset of 68000 (write)
        00B0 0000              	SetTASAddr		equ	$B00000		; Prime card for an offcard TAS instruction

                               	; Pointers to interrupt test routines
        00FF FF60              	SetL1Addr		equ $FFFF60
        00FF FF80              	TimeAddr		equ	$FFFF80
        00FF FFA0              	HostAddr		equ	$FFFFA0
        00FF FFC0              	IOPAddr			equ	$FFFFC0

                               	; test patterns
        5555 5555              	testWord1		equ	$55555555	; power-up RAM test data word
        AAAA AAAA              	testWord2		equ	$aaaaaaaa
        5A5A 5A5A              	testWord3		equ	$5a5a5a5a
        55AA 55AA              	testWord4		equ	$55aa55aa
        5A93 2BC7              	bTestPattern	equ	$5a932bc7	; test pattern in identifier block
        AAAA 5555              	testROMSig		equ	$aaaa5555	; PVT test ROM Signature

                               	; format header block offsets
        00FF FFFF              	fBlockLoc		equ	$ffffff		; 0, 1, 2, 3 bytelanes begins here
        0000 0000              	byteLanes		equ	0
        FFFF FFFB              	testPatLoc		equ	-5
        FFFF FFFA              	formatLoc		equ	-6
        FFFF FFF5              	CRCLoc			equ	-$b
        FFFF FFF1              	lengthLoc		equ	-$f
        FFFF FFEB              	CommIDLoc		equ -$15		;used to identify GMSIOP card application
        FFFF FFE9              	VendIDLoc		equ -$17		;used to identify specific hardware configuration

        0000 C3D2              	CommID			equ $c3d2		;GMSIOP card ROM identifier
        0000 0001              	MacID			equ 01			; Mac II ROM ID

                               	;Equates shared by asmlib.a & exceptions.a

        0000 00F7              	mode24mask	equ	$F7
        0000 0008              	mode32mask	equ	$8
        50F0 2000              	addrPort	equ	$50F02000		;32 bit hardware switch; no longer accessed directly
        0000 0CB2              	MMU32bit 	equ $0CB2			;(byte) boolean reflecting current 020 machine MMU mode
        00FF FFEC              	codePtr		equ	$FFFFEC
        0000 0A7C              	MyIntHndl	equ $a7c			;handle in 020 Application scratch memory
        0000 0A80              	AppScratch	equ	$a80			;last 4 bytes of appl scratch area

        A9FF                   	_Debugger		OPWORD	$A9FF
        A11E                   	_NewPtr 		OPWORD	$A100+30
        A01F                   	_DisposPtr		OPWORD	$A000+31
        A05D                   	_SwapMMUMode	OPWORD	$A05D		;from traps.a
        A075                   	_SIntInstall	OPWORD	$A075
        A076                   	_SIntRemove		OPWORD	$A076
        A9F2                   	_Launch			OPWORD  $A9F2

                               		MACRO
                               		_m32
                               		move.l	d0, -(a7)
                               		move.l	#1, d0
                               		_SwapMMUMode
                               		move.l	(a7)+, d0

MC68020 Assembler - Ver 2.88                                                                               14-Dec-88  Page   3
Copyright Apple Computer, Inc. 1984-1987

Loc   F Object Code     Addr  M	Source Statement

                               		ENDM

                               		MACRO
                               		_m24
                               		move.l	d0, -(a7)
                               		move.l	#0, d0
                               		_SwapMMUMode
                               		move.l	(a7)+, d0
                               		ENDM

                               		INCLUDE	'Application.h'
                               	;==================================================================================
                               	; File:		Application.h
                               	;
                               	; Function:	Application card ROM constants stored here
                               	;

        0042 0001              	bcpRIC		equ	$420001			; 8344 remote interface configuration register
        0040 0001              	bcpPC		equ	$400001			; Dummy address for writing to 8344 PC
        0040 0001              	bcpDRAM		equ	$400001			; 8344 Data RAM address base
        0040 7C15              	bcpGoodData	equ	$3E0A * 2 + bcpDRAM	; Test data
        0040 7C17              	bcpBadData	equ	$3E0B * 2 + bcpDRAM	; Bad data read back
        0040 7C19              	bcpErrAddrHi	equ	$3E0C * 2 + bcpDRAM	; Failed memory address, high order
        0040 7C1B              	bcpErrAddrLo	equ	$3E0D * 2 + bcpDRAM	; Failed memory address, low  order
        0040 7C1D              	bcpTestErr	equ	$3E0E * 2 + bcpDRAM	; BCP test error bits
        0040 7C1F              	bcpTestState	equ	$3E0F * 2 + bcpDRAM	; BCP test states

        0040 7C01              	bcpComm		equ	$3E00 * 2 + bcpDRAM	; BCP - 68k communication area
        0040 8001              	bcpDMEnd	equ	$4000 * 2 + bcpDRAM	; Last data memory + 1

                               	;
                               	; - RIC selections
                               	;

        0000 0034              	RIC_START	equ	$34		; Start 8344 execution
        0000 0030              	RIC_DRAM	equ	$30		; Select 8344 Data RAM
        0000 0034              	RIC_DRAM_RUN	equ	$34		; Select 8344 Data RAM and do not stop 8344
        0000 0031              	RIC_IMEM	equ	$31		; Select 8344 Instruction memory
        0000 0032              	RIC_PC_LO	equ	$32		; Select 8344 Program Counter low byte
        0000 0033              	RIC_PC_HI	equ	$33		; Select 8344 Program Counter high byte

                               	;
                               	; - BCP test states
                               	;

        0000 0000              	bcpIDLE		equ	$00		; BCP test not started
        0000 0001              	bcpRUNNING	equ	$01		; BCP test in progress
        0000 0002              	bcpDONE		equ	$02		; BCP test completed

                               	;
                               	; - BCP Tests entry points, low bytes
                               	;

        0000 0020              	BT_POR		equ	$20		; 8344 POR Test starts at 0020


                               	;
                               	; - BCP test error bits
                               	;

        0000 0001              	bcpRegErr	equ	$01		; BCP register test failed
        0000 0002              	bcpLoopErr	equ	$02		; BCP loop back test failed
        0000 0010              	bcpRamErr	equ	$10		; BCP data RAM test failed
        0000 0013              	bcpError	equ	bcpRegErr + bcpLoopErr + bcpRamErr

                               	;
                               	; Misc.
                               	;

        0000 0800              	BCP_IM_SIZE	equ	$800		; size of bcp instruction memory (I.M.)
        0000 1000              	bcp_rdback	equ	$0001000	; start location to store readback from 8344 I.M.
        0002 0000              	WaitBCPDone	equ	$00020000	; loop count waiting for 8344 to finish testing


        0000 5A6F              	VendID			equ $5a6f	;unofficial Zorro Vendor ID

MC68020 Assembler - Ver 2.88                                                                               14-Dec-88  Page   4
Copyright Apple Computer, Inc. 1984-1987

Loc   F Object Code     Addr  M	Source Statement


                               	;-----------  sResource Directory stuff	;<Id OF>
        0000 0001              	sRsrc_Board		EQU	1	;Board sResource
        0000 000A              	CommBoardId		EQU	$A	;Officially defined by Developer Technical Support
        0000 0004              	ROMRevLevel		equ	4	;ROM revision level (now D) must be < 9



        0000 0080              	sRsrc_CPU		EQU 128		;identify CPU & memory resources
        0000 0081              	sRsrc_Comm1		EQU 129		;comm type 1
        0000 0082              	sRsrc_Comm2		EQU 130		;comm type 2
        0000 0083              	sRsrc_Comm3		EQU 131		;comm type 3
        0000 0084              	sRsrc_Comm4		EQU 132		;comm type 4
        0000 008C              	sRsrc_sMemory		EQU 140		;2nd leved sResource (not seen directly by slot manager)

        0000 0096              	CatsMemory		EQU 150		;not defined by DTS, 2nd level sRrsource
        0000 0080              	MinorRAMAddr		EQU 128
        0000 0082              	MinorROMAddr		EQU 130
        0000 0084              	MinorDeviceAddr		EQU 132


        0000 000A              	CatCPU           EQU    $000A  ;
        0000 0001              	Typ68000         EQU    $0001  ;
        0000 FFFF              	DrSwNotThere     EQU    $FFFF  ;Apple MCP has 68K, no on-board driver
        0000 0001              	DrHwAMCP         EQU    $0001  ;First generation Apple MCP cards

        0000 0006              	CatCommunication EQU    $0006  ;mb  CatInterface?
        0000 0013              	Typ3270          EQU    $0013  ;vanilla 3270 for Zorro card 8/23/88
                               	;DrSwNotThere    EQU    $FFFF  ;Apple MCP has 68K, no on-board driver
                               	;DrHwAMCP        EQU    $0001  ;First generation Apple MCP cards

                               	;CatCommunication EQU    $0006  ;mb  CatInterface?
                               	;Typ3270         EQU    $0013  ;vanilla 3270 for Zorro card 8/23/88
                               	;DrSwNotThere    EQU    $FFFF  ;Apple MCP has 68K, no on-board driver
        0000 0006              	DrHwA3270_5250   EQU    $0006  ;Apple 3270/5250 NB card (Zorro)-implies 8344 chip

                               	;CatCommunication EQU    $0006  ;mb  CatInterface?
        0000 000A              	Typ5250    	 EQU    $000A  ;5250 protocol (actual DTS constant is Typ32705250)
                               	;DrSwNotThere    EQU    $FFFF  ;Apple MCP has 68K, no on-board driver
                               	;DrHwAMCP        EQU    $0001  ;First generation Apple MCP cards

                               	;CatCommunication EQU    $0006  ;mb  CatInterface?
                               	;Typ5250    	 EQU    $000A  ;5250 protocol (actual DTS constant is Typ32705250)
                               	;DrSwNotThere    EQU    $FFFF  ;Apple MCP has 68K, no on-board driver
                               	;DrHwA3270_5250  EQU    $0006  ;Apple 3270/5250 NB card (Zorro)-implies 8344 chip






                               	;Include files
                               		PRINT	ON


00000                          	CommROM	MAIN
00000                          		STRING 	C
00000
00000
00000                          	;===============================================================================
00000                          	; Power-On test
00000                          	; The following jsr PowerOn must be the first instruction of code in the ROM.
00000                          	; PowerOn tests RAM, ROM, & will then call the Vendor Powerup test defined in ApplPoweron.a
00000                          	;===============================================================================
00000
00000                          		IMPORT	PowerOn		;from powerup.a
00000
00000   4EBA 0000              		jsr	PowerOn
00004
00004                          	;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
00004                          	;		Resource	Directory
00004                          	;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
00004                          	;							<ID>	<OFFSET/DATA>
00004                          	_sRsrcDir	OSLstEntry  	sRsrc_Board,_sRsrc_Board	;<sRsrc_Board>  <Board sRsrc List offset>
00004   0100 001C             1					DC.L	(sRsrc_Board<<24)+((_sRsrc_Board-*)**$00FFFFFF)		;<C444/19nov86>

MC68020 Assembler - Ver 2.88                                                                               14-Dec-88  Page   5
Copyright Apple Computer, Inc. 1984-1987

Loc   F Object Code     Addr  M	Source Statement

00008                          		OSLstEntry	sRsrc_CPU, _sRsrc_CPU 	; defines CPU, MCP architecture
00008   8000 00A8             1					DC.L	(sRsrc_CPU<<24)+((_sRsrc_CPU-*)**$00FFFFFF)		;<C444/19nov86>
0000C                          		OSLstEntry	sRsrc_Comm1, _sRsrc_Comm1	;category Communications
0000C   8100 0148             1					DC.L	(sRsrc_Comm1<<24)+((_sRsrc_Comm1-*)**$00FFFFFF)		;<C444/19nov86>
00010                          		OSLstEntry	sRsrc_Comm2, _sRsrc_Comm2	;category Communications
00010   8200 0180             1					DC.L	(sRsrc_Comm2<<24)+((_sRsrc_Comm2-*)**$00FFFFFF)		;<C444/19nov86>
00014                          		OSLstEntry	sRsrc_Comm3, _sRsrc_Comm3	;category Communications
00014   8300 01B4             1					DC.L	(sRsrc_Comm3<<24)+((_sRsrc_Comm3-*)**$00FFFFFF)		;<C444/19nov86>
00018                          		OSLstEntry	sRsrc_Comm4, _sRsrc_Comm4	;categ…

Showing first 20,000 characters of 73,433 total. Open the full document →

MC68020 Assembler - Ver 2.88                                                                               14-Dec-88  Page   1
Copyright Apple Computer, Inc. 1984-1987

Loc   F Object Code     Addr  M	Source Statement


                               	;===================================================================================
                               	;
                               	; File:		ApplPowerOn.a
                               	;
                               	; Function:	Power on test for 8344 related circuitry
                               	;   {
                               	;	Test 8344 RIC register;
                               	;	Test 8344 Program Counter;
                               	;	Test 8344 Data RAM locations 0x3E00-0x3FFF with pattern FF then 00;
                               	;	Test 8344 Instruction memory with patterns FF then 00;
                               	;	Load 8344 test program;
                               	;	bcpTestState = IDLE;
                               	;	bcpTestErr = ER.RAM | ER.LOOP | ER.REG;
                               	;	Fill 0x3E10 to 0x3EFF with ripple pattern for TRx loopback test;
                               	;	Start 8344 test;
                               	;	Wait till bcpTestState != IDLE or timeout;
                               	;   }
                               	;
                               	; Input:	None
                               	;
                               	; Output:	None
                               	;
                               	; Update:	#VendPowerupMask ANDed to word in card location #TstStatus if no error
                               	;		($134) = 32 bit failure code if status indicates failure
                               	;
                               	; History:	12/03/87: initial version
                               	; M001 01/15/88 always set 'Fast Write' & 'Latched Read' when testing RIC
                               	; 	3/7/88   WHJW: moved all interrupt routines into this module
                               	;
                               	;===================================================================================

                               		INCLUDE	'CommDeclr.h'
                               	;*************************************************************************
                               	;
                               	; CommDeclr.h:
                               	;	Constants used for Smart card Diagnostics

        0007 FFFE              	STACK			EQU	$7FFFE		; offset of stack in card RAM
        0001 0000              	ROMSize			EQU	(64*1024)	; ROM = 64K

        0000 0000              	OFF				equ	0
        FFFF FFFF              	ON				equ	-1
        0000 0000              	PASS			equ	0
        FFFF FFFF              	FAIL			equ	-1
        0000 0001              	WAIT			equ 1

                               	; Delay constants in microseconds
        0000 0D00              	TimeDBRA		equ $D00		; (word) location: # of DBRA instructions/mSecond
        0000 01F4              	WaitCount		equ	500			; timeout  - wait for power_on finish
        0000 0004              	TimeCnt			equ	4			; timeout for IOP test
        0000 0010              	TimerWait 		equ	16			; timeout for Timer test
        0000 0004              	Delay			equ	4			; Reset delay

                               	; variable offsets into card RAM
        0000 0100              	WaitFlag		equ	$100		; power_on wait flag
        0000 0102              	TstStatus		equ	$102		; test status bit flags
        0000 0104              	TimeFlag		equ	$104		; flag for timer test
        0000 0106              	HostFlag		equ	$106		; flag for host reset test
        0000 0108              	ResetFlag		equ	$108		; flag to control reset code
        0000 010C              	IOPFlag			equ	$10C		; flag for IOP interrupt test
        0000 010E              	CRCCalcAddr 	equ	$10E		; ROM calculated CRC value
        0000 0112              	WriteLoc		equ	$112		; Location of Nubus write/read test
                               	;rteAddr			equ	$116	; rte for interrupt vectors (no longer used)
        0000 0118              	timeCountAddr 	equ	$118		; address of firmware timer counter
        0000 011C              	RAMSizeAddr		equ $11c		; Size of card RAM in bytes
        0000 0120              	TASStatusAddr	equ $120		; returns test & set card status to 020
        0000 0122              	NMRQFlag		equ	$122		; flag for NMRQ test
        0000 0128              	BusErrAddr		equ	$128		; flag for bus error
        0000 012C              	InitA5Addr		equ $12c		; Used for finding data block
        0000 0130              	CodeOffset		equ $130		; Used for finding code block
        0000 0134              	VendPowerStatus	equ $134		; return status from vendors power-up code
        0000 0138              	VendPrimaryStatus equ $138		; return status from vendors Primary init code
        0000 013C              	ExceptionPC		equ $13C		; PC stored here after exception takes place
        0000 0140              	ErrorAddr		equ $140		; data addr stored here after bus or addressing error

MC68020 Assembler - Ver 2.88                                                                               14-Dec-88  Page   2
Copyright Apple Computer, Inc. 1984-1987

Loc   F Object Code     Addr  M	Source Statement

        0000 0144              	RAMErrAddr		equ	$144		; if RAM error occurs, its address stored here
        0000 0148              	L1IntAddr		equ	$148		; Mac processor stores new Timer interrupt loc here;
                               									; then calls SetL1Interrupt to set it safely.
                               	; card space to $180 to $200 reserved for temporary data values only
        00E0 0000              	testROMAddr   	equ	$e00000		; location of Fremont board tester ROM
        0080 0008              	ROMversion		equ $800008		; location of Mac II ROM version number

                               	; Test status bit masks
        0000 FFFF              	testsDefined 	equ	$ffff		; currently defined test bits
        0000 FFFE              	DLTestMask		equ	$fffe		; sliding 5  data line test
        0000 FFFD              	RAMTestMask		equ	$fffd
        0000 FFFB              	testPatternMask equ	$fffb		; signals PROM burned incorrectly
        0000 FFF7              	CRCTestMask		equ	$fff7		; Clears CRC test bit
        0000 FFEF              	VendPowerupMask equ	$ffef
        0000 001F              	PowerMask		equ	$1F
        FFFF FFDF              	BusMask			equ	$FFFFFFDF	; clears Nubus write/read test bit
        FFFF FFBF              	HostMask		equ	$FFFFFFBF	; clears host reset test bit
        FFFF FF7F              	TimeMask		equ	$FFFFFF7F	; clears timer test bit
        FFFF FEFF              	IOPMask			equ	$FFFFFEFF	; clears IOP test bit
        FFFF FDFF              	VendMask		equ	$FFFFFDFF	; clears vendor test bit
        FFFF FBFF              	NMRQMask		equ $FFFFFBFF	; clears NMRQ test bit

                               	; Card control switch offsets
        00C0 0000              	ExtReg			equ	$C00000		; Nubus extension register (write) or unreset (read)
        00C0 0002              	TimerSet		equ	$C00002		; Timer interrupt switch (read)
        00C0 0008              	ClrIOPIntr 		equ	$C00008		; Clear Interrupt IOP request (read)
        00C0 000A              	SetIOPIntr 		equ	$C0000A		; Set Interrupt IOP request (read)
        00C0 0004              	ClrHostIntr 	equ	$C00004		; Clear Host Interrupt request (read)
        00C0 0006              	SetHostIntr 	equ	$C00006		; Set Host Interrupt request (read)
        00F0 0000              	Reset			equ	$F00000		; programmed reset of 68000 (write)
        00B0 0000              	SetTASAddr		equ	$B00000		; Prime card for an offcard TAS instruction

                               	; Pointers to interrupt test routines
        00FF FF60              	SetL1Addr		equ $FFFF60
        00FF FF80              	TimeAddr		equ	$FFFF80
        00FF FFA0              	HostAddr		equ	$FFFFA0
        00FF FFC0              	IOPAddr			equ	$FFFFC0

                               	; test patterns
        5555 5555              	testWord1		equ	$55555555	; power-up RAM test data word
        AAAA AAAA              	testWord2		equ	$aaaaaaaa
        5A5A 5A5A              	testWord3		equ	$5a5a5a5a
        55AA 55AA              	testWord4		equ	$55aa55aa
        5A93 2BC7              	bTestPattern	equ	$5a932bc7	; test pattern in identifier block
        AAAA 5555              	testROMSig		equ	$aaaa5555	; PVT test ROM Signature

                               	; format header block offsets
        00FF FFFF              	fBlockLoc		equ	$ffffff		; 0, 1, 2, 3 bytelanes begins here
        0000 0000              	byteLanes		equ	0
        FFFF FFFB              	testPatLoc		equ	-5
        FFFF FFFA              	formatLoc		equ	-6
        FFFF FFF5              	CRCLoc			equ	-$b
        FFFF FFF1              	lengthLoc		equ	-$f
        FFFF FFEB              	CommIDLoc		equ -$15		;used to identify GMSIOP card application
        FFFF FFE9              	VendIDLoc		equ -$17		;used to identify specific hardware configuration

        0000 C3D2              	CommID			equ $c3d2		;GMSIOP card ROM identifier
        0000 0001              	MacID			equ 01			; Mac II ROM ID

                               	;Equates shared by asmlib.a & exceptions.a

        0000 00F7              	mode24mask	equ	$F7
        0000 0008              	mode32mask	equ	$8
        50F0 2000              	addrPort	equ	$50F02000		;32 bit hardware switch; no longer accessed directly
        0000 0CB2              	MMU32bit 	equ $0CB2			;(byte) boolean reflecting current 020 machine MMU mode
        00FF FFEC              	codePtr		equ	$FFFFEC
        0000 0A7C              	MyIntHndl	equ $a7c			;handle in 020 Application scratch memory
        0000 0A80              	AppScratch	equ	$a80			;last 4 bytes of appl scratch area

        A9FF                   	_Debugger		OPWORD	$A9FF
        A11E                   	_NewPtr 		OPWORD	$A100+30
        A01F                   	_DisposPtr		OPWORD	$A000+31
        A05D                   	_SwapMMUMode	OPWORD	$A05D		;from traps.a
        A075                   	_SIntInstall	OPWORD	$A075
        A076                   	_SIntRemove		OPWORD	$A076

MC68020 Assembler - Ver 2.88                                                                               14-Dec-88  Page   3
Copyright Apple Computer, Inc. 1984-1987

Loc   F Object Code     Addr  M	Source Statement

        A9F2                   	_Launch			OPWORD  $A9F2

                               		MACRO
                               		_m32
                               		move.l	d0, -(a7)
                               		move.l	#1, d0
                               		_SwapMMUMode
                               		move.l	(a7)+, d0
                               		ENDM

                               		MACRO
                               		_m24
                               		move.l	d0, -(a7)
                               		move.l	#0, d0
                               		_SwapMMUMode
                               		move.l	(a7)+, d0
                               		ENDM

                               		INCLUDE 'Application.h'
                               	;==================================================================================
                               	; File:		Application.h
                               	;
                               	; Function:	Application card ROM constants stored here
                               	;

        0042 0001              	bcpRIC		equ	$420001			; 8344 remote interface configuration register
        0040 0001              	bcpPC		equ	$400001			; Dummy address for writing to 8344 PC
        0040 0001              	bcpDRAM		equ	$400001			; 8344 Data RAM address base
        0040 7C15              	bcpGoodData	equ	$3E0A * 2 + bcpDRAM	; Test data
        0040 7C17              	bcpBadData	equ	$3E0B * 2 + bcpDRAM	; Bad data read back
        0040 7C19              	bcpErrAddrHi	equ	$3E0C * 2 + bcpDRAM	; Failed memory address, high order
        0040 7C1B              	bcpErrAddrLo	equ	$3E0D * 2 + bcpDRAM	; Failed memory address, low  order
        0040 7C1D              	bcpTestErr	equ	$3E0E * 2 + bcpDRAM	; BCP test error bits
        0040 7C1F              	bcpTestState	equ	$3E0F * 2 + bcpDRAM	; BCP test states

        0040 7C01              	bcpComm		equ	$3E00 * 2 + bcpDRAM	; BCP - 68k communication area
        0040 8001              	bcpDMEnd	equ	$4000 * 2 + bcpDRAM	; Last data memory + 1

                               	;
                               	; - RIC selections
                               	;

        0000 0034              	RIC_START	equ	$34		; Start 8344 execution
        0000 0030              	RIC_DRAM	equ	$30		; Select 8344 Data RAM
        0000 0034              	RIC_DRAM_RUN	equ	$34		; Select 8344 Data RAM and do not stop 8344
        0000 0031              	RIC_IMEM	equ	$31		; Select 8344 Instruction memory
        0000 0032              	RIC_PC_LO	equ	$32		; Select 8344 Program Counter low byte
        0000 0033              	RIC_PC_HI	equ	$33		; Select 8344 Program Counter high byte

                               	;
                               	; - BCP test states
                               	;

        0000 0000              	bcpIDLE		equ	$00		; BCP test not started
        0000 0001              	bcpRUNNING	equ	$01		; BCP test in progress
        0000 0002              	bcpDONE		equ	$02		; BCP test completed

                               	;
                               	; - BCP Tests entry points, low bytes
                               	;

        0000 0020              	BT_POR		equ	$20		; 8344 POR Test starts at 0020


                               	;
                               	; - BCP test error bits
                               	;

        0000 0001              	bcpRegErr	equ	$01		; BCP register test failed
        0000 0002              	bcpLoopErr	equ	$02		; BCP loop back test failed
        0000 0010              	bcpRamErr	equ	$10		; BCP data RAM test failed
        0000 0013              	bcpError	equ	bcpRegErr + bcpLoopErr + bcpRamErr

                               	;
                               	; Misc.

MC68020 Assembler - Ver 2.88                                                                               14-Dec-88  Page   4
Copyright Apple Computer, Inc. 1984-1987

Loc   F Object Code     Addr  M	Source Statement

                               	;

        0000 0800              	BCP_IM_SIZE	equ	$800		; size of bcp instruction memory (I.M.)
        0000 1000              	bcp_rdback	equ	$0001000	; start location to store readback from 8344 I.M.
        0002 0000              	WaitBCPDone	equ	$00020000	; loop count waiting for 8344 to finish testing


        0000 5A6F              	VendID			equ $5a6f	;unofficial Zorro Vendor ID

                               	;-----------  sResource Directory stuff	;<Id OF>
        0000 0001              	sRsrc_Board		EQU	1	;Board sResource
        0000 000A              	CommBoardId		EQU	$A	;Officially defined by Developer Technical Support
        0000 0004              	ROMRevLevel		equ	4	;ROM revision level (now D) must be < 9



        0000 0080              	sRsrc_CPU		EQU 128		;identify CPU & memory resources
        0000 0081              	sRsrc_Comm1		EQU 129		;comm type 1
        0000 0082              	sRsrc_Comm2		EQU 130		;comm type 2
        0000 0083              	sRsrc_Comm3		EQU 131		;comm type 3
        0000 0084              	sRsrc_Comm4		EQU 132		;comm type 4
        0000 008C              	sRsrc_sMemory		EQU 140		;2nd leved sResource (not seen directly by slot manager)

        0000 0096              	CatsMemory		EQU 150		;not defined by DTS, 2nd level sRrsource
        0000 0080              	MinorRAMAddr		EQU 128
        0000 0082              	MinorROMAddr		EQU 130
        0000 0084              	MinorDeviceAddr		EQU 132


        0000 000A              	CatCPU           EQU    $000A  ;
        0000 0001              	Typ68000         EQU    $0001  ;
        0000 FFFF              	DrSwNotThere     EQU    $FFFF  ;Apple MCP has 68K, no on-board driver
        0000 0001              	DrHwAMCP         EQU    $0001  ;First generation Apple MCP cards

        0000 0006              	CatCommunication EQU    $0006  ;mb  CatInterface?
        0000 0013              	Typ3270          EQU    $0013  ;vanilla 3270 for Zorro card 8/23/88
                               	;DrSwNotThere    EQU    $FFFF  ;Apple MCP has 68K, no on-board driver
                               	;DrHwAMCP        EQU    $0001  ;First generation Apple MCP cards

                               	;CatCommunication EQU    $0006  ;mb  CatInterface?
                               	;Typ3270         EQU    $0013  ;vanilla 3270 for Zorro card 8/23/88
                               	;DrSwNotThere    EQU    $FFFF  ;Apple MCP has 68K, no on-board driver
        0000 0006              	DrHwA3270_5250   EQU    $0006  ;Apple 3270/5250 NB card (Zorro)-implies 8344 chip

                               	;CatCommunication EQU    $0006  ;mb  CatInterface?
        0000 000A              	Typ5250    	 EQU    $000A  ;5250 protocol (actual DTS constant is Typ32705250)
                               	;DrSwNotThere    EQU    $FFFF  ;Apple MCP has 68K, no on-board driver
                               	;DrHwAMCP        EQU    $0001  ;First generation Apple MCP cards

                               	;CatCommunication EQU    $0006  ;mb  CatInterface?
                               	;Typ5250    	 EQU    $000A  ;5250 protocol (actual DTS constant is Typ32705250)
                               	;DrSwNotThere    EQU    $FFFF  ;Apple MCP has 68K, no on-board driver
                               	;DrHwA3270_5250  EQU    $0006  ;Apple 3270/5250 NB card (Zorro)-implies 8344 chip



                               		ENTRY	bcpCodes

00000                          	VendorPowerUp:	PROC	EXPORT		; WHJW: mod to facilitate modular structure
00000 G 007C 0700              		or.w	#$0700, SR		; disable interrupts 0-7
00004   4EBA 0096       0009C  		jsr	zt_RIC			; test 8344 RIC
00008   6600 0090       0009A  		bne	zt_err			; skip if error
0000C
0000C   4EBA 00CC       000DA  		jsr	zt_PC			; test 8344 program counter
00010   6600 0088       0009A  		bne	zt_err			; skip if error
00014
00014 G 247C 0040 7C01         		move.l	#bcpComm, A2		; point to location 3E00 of data memory
0001A G 267C 0040 8001         		move.l	#bcpDMEnd, A3		; ending location
00020   4EBA 011C       0013E  		jsr	zt_RAM			; test interface area (0x3E00 - 0x3FFF)
00024   6600 0074       0009A  		bne	zt_err			; skip if error
00028
00028   4EBA 016C       00196  		jsr	zt_IMem			; test 8344 instruction memory
0002C   666C            0009A  		bne.s	zt_err			; skip if error
0002E
0002E   47FA 0000              		lea	bcpCodes, A3		; A3 = address of 8344 code records

MC68020 Assembler - Ver 2.88                                                                               14-Dec-88  Page   5
Copyright Apple Computer, Inc. 1984-1987

Loc   F Object Code     Addr  M	Source Statement

00032   4EBA 01DA       0020E  		jsr	load_BCP		; load test code to 8344
00036   6662            0009A  		bne.s	zt_err			; skip if error
00038
00038                          	;	movea.l	#bcp_readback, A3  	; A3 = address of buf to store readback
00038                          	;	jsr	read_BCP	   	; read 8344 instructions back
00038
00038                          	;---------------------------------------
00038                          	; - Set BCP Test State to IDLE, error flag indicates all error bits set
00038                          	; - Start 8344 execution
00038                          	;---------------------------------------
00038
00038   227C 0042 0001         		movea.l	#bcpRIC, A1…

Showing first 20,000 characters of 80,747 total. Open the full document →

;===================================================================================
;
; File:		ApplPowerOn.a
;
; Function:	Power on test for 8344 related circuitry 
;   {
;	Test 8344 RIC register;
;	Test 8344 Program Counter;
;	Test 8344 Data RAM locations 0x3E00-0x3FFF with pattern FF then 00;
;	Test 8344 Instruction memory with patterns FF then 00;
;	Load 8344 test program;
;	bcpTestState = IDLE;
;	bcpTestErr = ER.RAM | ER.LOOP | ER.REG;
;	Fill 0x3E10 to 0x3EFF with ripple pattern for TRx loopback test;
;	Start 8344 test;
;	Wait till bcpTestState != IDLE or timeout;
;   }
;
; Input:	None
;
; Output:	None
;
; Update:	#VendPowerupMask ANDed to word in card location #TstStatus if no error
;		($134) = 32 bit failure code if status indicates failure
;
; History:	12/03/87: initial version
; M001 01/15/88 always set 'Fast Write' & 'Latched Read' when testing RIC
; 	3/7/88   WHJW: moved all interrupt routines into this module
;
;===================================================================================

	INCLUDE	'CommDeclr.h'
	INCLUDE 'Application.h'
	ENTRY	bcpCodes
	
VendorPowerUp:	PROC	EXPORT		; WHJW: mod to facilitate modular structure
	or.w	#$0700, SR		; disable interrupts 0-7
	jsr	zt_RIC			; test 8344 RIC
	bne	zt_err			; skip if error
	
	jsr	zt_PC			; test 8344 program counter
	bne	zt_err			; skip if error
	
	move.l	#bcpComm, A2		; point to location 3E00 of data memory
	move.l	#bcpDMEnd, A3		; ending location
	jsr	zt_RAM			; test interface area (0x3E00 - 0x3FFF)
	bne	zt_err			; skip if error
	
	jsr	zt_IMem			; test 8344 instruction memory
	bne.s	zt_err			; skip if error
	
	lea	bcpCodes, A3		; A3 = address of 8344 code records
	jsr	load_BCP		; load test code to 8344
	bne.s	zt_err			; skip if error
		
;	movea.l	#bcp_readback, A3  	; A3 = address of buf to store readback
;	jsr	read_BCP	   	; read 8344 instructions back

;---------------------------------------
; - Set BCP Test State to IDLE, error flag indicates all error bits set
; - Start 8344 execution
;---------------------------------------

	movea.l	#bcpRIC, A1	   	; address of 8344 RIC
	moveq	#RIC_DRAM, D0		; select Data memory
	move.b	D0, (A1)	   	;
	moveq	#bcpIDLE, D1	   	; set BCP test state = IDLE
	movea.l	#bcpTestState, A2  	;
	move.b	D1, (A2)	   	;
				
	moveq	#bcpError, D1		; init bcpTestErr with all error bits set
	movea.l	#bcpTestErr, A2		;
	move.b	D1, (A2)		;

	moveq	#RIC_PC_LO, D0		; select 8344 PC 
	move.b	D0, (A1)		;
	moveq	#BT_POR, D1		; 8344 POR test entry
	move.b	D1, (A2)		;
	moveq	#RIC_PC_HI, D0		; 
	move.b	D0, (A1)		;
	move.b	#00, (A2)		;
				
	moveq	#RIC_START, D0		; start 8344 execution
	move.b	D0, (A1)		;
				
;---------------------------------------
; - Wait for 8344 finish its testing
;---------------------------------------

	move.l	#WaitBCPDone, D2  	; loop count waiting for 8344 finish testing
@30:
	moveq	#RIC_DRAM_RUN, D0	; select Data memory
	move.b	D0, (A1)	  	;
	movea.l	#bcpTestState, A2 	;
	cmp.b	#bcpDONE, (A2)	 	; check if 8344 finish testing
	beq.s	zt_rtn		 	; exit loop if yes
	subq.l	#1, D2			; decrement count
	bne.s	@30			; keep checking till timeout
	
;
; - Check if 8344 test error
;

	moveq	#RIC_DRAM, D0		; select Data memory & stop 8344
	move.b	D0, (A1)	   	;
	movea.l	#bcpTestErr, A2		; test error location
	cmp.b	#0, (A2)		; get 8344 test error indicator
	bne.s	zt_err			; skip if error
	
;---------------------------------------
; - No error exit
;---------------------------------------

zt_rtn:
	movea.l	#TstStatus, A0	;address in low board memory
	and.w	#VendPowerupMask, (A0)	; passed! 

;---------------------------------------
; -  exit
;---------------------------------------

zt_err:
	rts


	EJECT

;===================================================================================
;
; Name:		Test RIC
;
; Function:	Test 8344 Remote Interface Configuration register 
;
; Input:	None
;
; Output:	Z flag set   => no error
;		Z flag clear => error (D1 = data written; D2 = data read back)
;
; Update:	None
;
; History:	12/03/87: initial version
; M001 01/15/88 always set 'Fast Write' & 'Latched Read' when testing RIC
;
;===================================================================================

zt_RIC:	
	movea.l	#bcpRIC, A1	; address of 8344 RIC
	moveq	#$30, D1	; write 30				;;;M001
	move.b	D1, (A1)	; 
	move.b	(A1), D2	; read back
	andi.b	#$7F, D2	; MSB is read only
	cmp.b	D1, D2		; compare
	bne.s	@90		; jump if error
				
	moveq	#$31, D1	; write 31				;;;M001
	move.b	D1, (A1)	;
	move.b	(A1), D2	; read back
	andi.b	#$7F, D2	;
	cmp.b	D1, D2		; compare
	bne.s	@90		; jump if error
				
	moveq	#$32, D1	; write 32				;;;M001
	move.b	D1, (A1)	;
	move.b	(A1), D2	; read back
	andi.b	#$7F, D2	;
	cmp.b	D1, D2		; compare
	bne.s	@90		; jump if error
				
	moveq	#$33, D1	; write 33				;;;M001
	move.b	D1, (A1)	; 
	move.b	(A1), D2	; read back
	andi.b	#$7F, D2	;
	cmp.b	D1, D2		; compare
@90:
	rts
	
	EJECT

;===================================================================================
;
; Name:		zt_PC
;
; Function:	Test 8344 Program Counter
;
; Input:	None
;
; Output:	Z flag set   => no error
;		Z flag clear => error (D1 = data written; D2 = data read back;
;				       A2 = failed address)
;
; Update:	None
;
; History:	12/03/87: initial version
;
;===================================================================================
				
zt_PC:
	movea.l	#bcpRIC, A1	; address of 8344 RIC
	moveq	#RIC_PC_LO, D0	; select PC low
	move.b	D0, (A1)	;
	movea.l	#bcpPC, A2	; dummy address for writing to 8344 PC

	move.b	#$FF,D1		; pattern 0xFF
	move.b	D1, (A2)	; write to PC low
	cmp.b	(A2), D1	; read back check
	bne.s	@90		; jump if error
				
	moveq	#$55,D1		; pattern 0x55
	move.b	D1, (A2)	; write to PC low
	cmp.b	(A2), D1	; read back check
	bne.s	@90		; jump if error
			
	move.b	#$AA,D1		; pattern 0xAA
	move.b	D1, (A2)	; write to PC low
	cmp.b	(A2), D1	; read back check
	bne.s	@90		; jump if error
				
	move.b	D1, (A2)	; write to PC low
	cmp.b	(A2), D1	; read back check
	bne.s	@90		; jump if error
				
	moveq	#RIC_PC_HI, D0	; select PC high
	move.b	D0, (A1)	;

	move.b	#$FF,D1		; pattern 0xFF
	move.b	D1, (A2)	; write to PC low
	cmp.b	(A2), D1	; read back check
	bne.s	@90		; jump if error
				
	moveq	#$55,D1		; pattern 0x55
	move.b	D1, (A2)	; write to PC low
	cmp.b	(A2), D1	; read back check
	bne.s	@90		; jump if error
				
	move.b	#$AA,D1		; pattern 0xAA
	move.b	D1, (A2)	; write to PC low
	cmp.b	(A2), D1	; read back check
	bne.s	@90		; jump if error
				
	moveq	#$00,D1		; pattern 0x00
	move.b	D1, (A2)	; write to PC low
	cmp.b	(A2), D1	; read back check
	bne.s	@90		; jump if error
	
	rts			; good return	
@90:
	move.b	(A2), D2	; D2 = bad data
	move.b	#1, D3		; insure Z = 0
	rts			; return
	
	EJECT

;===================================================================================
;
; Name:		zt_RAM
;
; Function:	Test 8344 Data Memory 
;
; Input:	A2 = starting RAM address
;		A3 = ending RAM address + 1
;
; Output:	Z flag set   => no error
;		Z flag clear => error (D1 = data written; D2 = data read back;
;				       A2 = failed address)
;
; Update:	None
;
; History:	12/03/87: initial version
;
;===================================================================================
				
zt_RAM:
	movea.l	#bcpRIC, A1	; address of 8344 RIC
	move.l	A2, D3		; save starting location
	moveq	#RIC_DRAM, D0	; select Data memory
	move.b	D0, (A1)	;
	move.b	#$FF,D1		; data pattern
@1:
	move.b	D1, (A2)	; write to memory
	cmp.b	(A2), D1	; read it back check
	bne.s	@90		; jump if errror
				
	addq.l	#2, A2		; addr.ptr++
	cmp.l	A3, A2		; check if reached end
	bne.s	@1
				
	movea.l	D3, A2		; reset pointer to where it started
	moveq	#$55,D1		; data pattern
@2:
	move.b	D1, (A2)	; write to memory
	cmp.b	(A2), D1	; read it back check
	bne.s	@90		; jump if errror
				
	addq.l	#2, A2		; addr.ptr++
	cmp.l	A3, A2		; check if reached end
	bne.s	@2
					
	movea.l	D3, A2		; reset pointer to where it started
	move.b	#$AA,D1		; data pattern
@3:
	move.b	D1, (A2)	; write to memory
	cmp.b	(A2), D1	; read it back check
	bne.s	@90		; jump if errror
				
	addq.l	#2, A2		; addr.ptr++
	cmp.l	A3, A2		; check if reached end
	bne.s	@3
				
	movea.l	D3, A2		; reset pointer to where it started
	moveq	#$00,D1		; data pattern
@4:
	move.b	D1, (A2)	; write to memory
	cmp.b	(A2), D1	; read it back check
	bne.s	@90		; jump if errror
				
	addq.l	#2, A2		; addr.ptr++
	cmp.l	A3, A2		; check if reached end
	bne.s	@4
	
	rts			; good return
@90:
	move.b	(A2), D2	; D2 = data read back
	move.b	#1, D3		; insure Z = 0
	rts			; return
	
	EJECT

;===================================================================================
;
; Name:		zt_IMem
;
; Function:	Test 8344 instruction memory
;
; Input:	None
;
; Output:	Z flag set   => no error
;		Z flag clear => error (D1 = data written; D2 = data read back;
;				       A2 = failed address)
;
; Update:	None
;
; History:	12/03/87: initial version
;
;===================================================================================
				
zt_IMem:
	movea.l	#bcpRIC, A1	; address of 8344 RIC
	movea.l	#bcpPC, A2	; dummy address for writing to 8344 PC
	move.b	#$FF, D3	; D3 = test pattern
	jsr	bcpimtest	; test 
	bne.s	@90		; jump if error
				
	move.b	#$AA, D3	; D3 = test pattern
	jsr	bcpimtest	; test 
	bne.s	@90		; jump if error
				
	move.b	#$55, D3	; D3 = test pattern
	jsr	bcpimtest	; test 
	bne.s	@90		; jump if error
				
	move.b	#$00, D3	; D3 = test pattern
	jsr	bcpimtest	; test 
@90:
	rts			; return
	
	EJECT

;===================================================================================
;
; Name:		bcpimtest
;
; Function:	Test 8344 instruction memory with a pattern
;
; Input:	D3 = pattern byte
;		A1 = address of 8344 RIC
;		A2 = dummy address to write instruction memory
;
; Output:	Z flag set   => no error
;		Z flag clear => error (D1 = data written; D2 = data read back;
;				       A2 = failed address)
;
; Update:	None
;
; History:	12/03/87: initial version
;
;===================================================================================

bcpimtest:
	moveq	#RIC_PC_LO, D0	; select PC low
	move.b	D0, (A1)	;
	move.b	#$00, (A2)	; write PC low byte = 00
	moveq	#RIC_PC_HI, D0	; select PC high
	move.b	D0, (A1)	;
	move.b	#$00, (A2)	; write PC high byte = 00
	moveq	#RIC_IMEM, D0	; select instruction memory
	move.b	D0, (A1)	  ;
	move.l	#BCP_IM_SIZE, D4  ; D4 = 8344 instruction memory size
@1006:
	move.b	D3, (A2)	; write low byte
	move.b	D3, (A2)	; write high byte
	subq.l	#1, d4		; decrement count
	bne.s	@1006		; till end of instruction memory

	moveq	#RIC_PC_LO, D0	; select PC low
	move.b	D0, (A1)	;
	move.b	#$00, (A2)	; write PC low byte = 00

	moveq	#RIC_PC_HI, D0	; select PC high
	move.b	D0, (A1)	;
	move.b	#$00, (A2)	; write PC high byte = 00
	moveq	#RIC_IMEM, D0	; select instruction memory
	move.b	D0, (A1)				;
	move.l	#BCP_IM_SIZE, D4  ; D4 = 8344 instruction memory size
@1008:
	move.b	(A2), D1	; D1 = low byte read back
	move.b	(A2), D2	; D2 = high byte read back
	cmp.b	D1, D3		; check if equal
	bne.s	@1009
	cmp.b	D2, D3		; check if equal
	bne.s	@1009
	subq.l	#1, d4		; decrement count
	bne.s	@1008		; till end of instruction memory

@1009:	
	rts			; return to caller
				
	EJECT

;===================================================================================
;
; Name:		load_BCP
;
; Function:	Load 8344 codes to its instruction memory
;		First word (record) of the code table must be FFFF which indicates
;		next record is the Program Counter record.
;		The third record and records thereafter (until it is FFFFF) are
;		records of the codes to be downloaded to 8344 starting from the PC.
;		End of the code is terminated by 2 consecutive records of FFFF.	
;
; Input:	None
;
; Output:	Z flag set   => no error
;		Z flag clear => error 
;
; Update:	None
;
; History:	12/03/87: initial version
;
;===================================================================================

load_BCP:
	movea.l	#bcpRIC, A1	; address of 8344 RIC
	lea	bcpCodes, A3	; A3 -> 8344 codes in PROM
	move.w	#$FFFF, D4	; D4 = 0xFFFF
	cmp.w	(A3)+, D4	; check if PC indicator record
	bne.s	@90		; error if not
				
	movea.l	#bcpPC, A2	; dummy address for writing to 8344 PC
@10:
	move.w	(A3)+, D3	; D3 = next record
	cmp.w	D3, D4		; check if 0xFFFF
	beq.s	@90		; if yes, finished download
				; otherwise, it's PC for the 8344
	moveq	#RIC_PC_LO, D0	; select PC low
	move.b	D0, (A1)	;
	move.b	D3, (A2)	; write PC low byte

	lsr	#8, D3		; D3 = high order of 8344 PC
	moveq	#RIC_PC_HI, D0	; select PC high
	move.b	D0, (A1)	;
	move.b	D3, (A2)	; write PC high byte
	moveq	#RIC_IMEM, D0	; select instruction memory
	move.b	D0, (A1)	;
@12:
	move.w	(A3)+, D3	; get next record				
	cmp.w	D3, D4		; check if 0xFFFF
	beq.s	@10		; load PC if yes
				
	move.b	D3, (A2)	; write low byte to instruction memory
	lsr	#8, D3		; get high byte to the right
	move.b	D3, (A2)	; write high byte to the instruction memory
	bra.s	@12		; go get next record
@90:
	rts			; return
	
	EJECT

;===================================================================================
;
; Name:		read_BCP
;
; Function:	Read 8344 codes from its instruction memory for debugging purpose.
;
; Input:	None
;
; Output:	Z flag set   => no error
;		Z flag clear => error 
;
; Update:	None
;
; History:	12/03/87: initial version
;
;===================================================================================

read_BCP:
	movea.l	#bcpRIC, A1	; address of 8344 RIC
	movea.l	#bcpPC, A2	; dummy address for accessing to 8344 PC
	move.l	#BCP_IM_SIZE, D3; D3 = 8344 instruction memory size in words
	lsl.l	#1, D3		; D3 = number of bytes
	movea.l	#bcp_rdback, A3	; A3 = buf address to store readbacks
	moveq	#RIC_PC_LO, D0	; select PC low
	move.b	D0, (A1)	;
	move.b	#0, (A2)	; write PC low byte = 00
	moveq	#RIC_PC_HI, D0	; select PC high
	move.b	D0, (A1)	;
	move.b	#0, (A2)	; write PC high byte = 00
	moveq	#RIC_IMEM, D0	; select instruction memory
	move.b	D0, (A1)	;
@12:
	move.b	(A2), D2	; read back
	move.b	D2, (A3)+	; store in buffer
	subi.l	#1, D3		; decrement count
	bne.s	@12
@90:
	rts			; return
	
	EJECT
		
L1Interrupt	Proc	Export	
		move.l	a1, -(sp)		; save reg
		movea.l	#$c00002, a1	
		move.w	(a1), a1 		; clear timer interrupt
		movea.l	#timeCountAddr, a1
		addq.l	#1, (a1) 		; incr timer location
		move.l	(sp)+, a1		; restore reg
		rte
			  
L2Interrupt	PROC	EXPORT
		move.l	a0, -(sp)
		movea.l	#ClrIOPIntr, a0
		move.l	(a0), a0		;read clears interrupt
		move.l	(sp)+, a0
		rte				;GMSIOP interrupt
		
L3Interrupt	PROC	EXPORT			; WHJW: mod to facilitate modular structure
		movem.l	d0/a1, -(sp)
		movea.l	#bcpRIC, a1		;address of 8344 RIC
		moveq	#RIC_DRAM_RUN, d0	;select data memory
		add	#$80, d0
		move.b	d0, (a1)		;toggle interrupt activate line
		movem.l	(sp)+, d0/a1
		rte
		
L4Interrupt	PROC	EXPORT
		rte				;not used on Zorro card
L5Interrupt	PROC	EXPORT
		rte				;not used on Zorro card
L6Interrupt	PROC	EXPORT
		rte				;not used on Zorro card
		
L7Interrupt	PROC	EXPORT			;NMI interrupt
		move.w	(sp)+, a0		;pop sr & forget it
		move.l	(sp)+, a0		;pop return address & forget it
		movea.l	#$ff0004, a0		;location of power-up code starting addr
		move.l	(a0), a0
		jmp	(a0)			;assume supr. stack ptr set by caller
		rte
		
;===================================================================================
; Entry:	(Status indicator routines)
;
; Function:	
;	When execution of 68000 power-on begins, ShowInProgress (which could turn on all LEDs)
;	is called, indicating that the test is in progress.  If primary init crashes
;	it will then be evident that testing did not complete.  If any tests fail,
;	the routine ShowFail is called (perhaps to leave on a red LED), and if all 
;	self-tests pass, the routine ShowPass is called (perhaps to leave on a red LED). 
;	ShowOff is called to turn off all indicator status.
;
;	Note that these routines differ from the 4 status indicator routines in
;	ApplPrimaryInit.a in that they are not performed accross NuBus, but by the
;	cards 68000.
;   
;===================================================================================

ShowInProgress:			;turn on red & green LED or do whatever to indicate test running
	move.l	a1, -(sp)	;save & restore any registers changed
	move.l	#$600001, a1	;currently defined Zorro LED control register
	move.b	#$3, (a1) 	;write to LED control register (turn on red & green)
	move.l	(sp)+, a1
	rts			
	
ShowPass:			;turn on green LED or do whatever to indicate good status
	move.l	a1, -(sp)	;save & restore any registers changed
	move.l	#$600001, a1	;currently defined Zorro LED control register
	move.b	#$1, (a1) 	;write to LED control register (turn on green only)
	move.l	(sp)+, a1
	rts	
	
ShowFail:			;turn on red LED or do whatever to indicate failure
	move.l	a1, -(sp)	;save & restore any registers changed
	move.l	#$600001, a1	;currently defined Zorro LED control register
	move.b	#$2, (a1) 	;write to LED control register (turn on red only)
	move.l	(sp)+, a1
	rts	
	
ShowOff:			;turn off green & red LED or all status indicators
	move.l	a1, -(sp)	;save & restore any registers changed
	move.l	#$600001, a1	;currently defined Zorro LED control register
	move.b	#$0, (a1) 	;write to LED control register (turn off red & green)
	move.l	(sp)+, a1
	rts	
	
	END
;---------------
; 8344 Codes
;---------------

bcpCodes	PROC

	INCLUDE		'btest.68k'	

	EJECT
	END

;==================================================================================
; File:		Application.h
;
; Function:	Application card ROM constants stored here
;

bcpRIC		equ	$420001			; 8344 remote interface configuration register
bcpPC		equ	$400001			; Dummy address for writing to 8344 PC
bcpDRAM		equ	$400001			; 8344 Data RAM address base
bcpGoodData	equ	$3E0A * 2 + bcpDRAM	; Test data 
bcpBadData	equ	$3E0B * 2 + bcpDRAM	; Bad data read back
bcpErrAddrHi	equ	$3E0C * 2 + bcpDRAM	; Failed memory address, high order
bcpErrAddrLo	equ	$3E0D * 2 + bcpDRAM	; Failed memory address, low  order
bcpTestErr	equ	$3E0E * 2 + bcpDRAM	; BCP test error bits
bcpTestState	equ	$3E0F * 2 + bcpDRAM	; BCP test states

bcpComm		equ	$3E00 * 2 + bcpDRAM	; BCP - 68k communication area
bcpDMEnd	equ	$4000 * 2 + bcpDRAM	; Last data memory + 1

;
; - RIC selections
;

RIC_START	equ	$34		; Start 8344 execution
RIC_DRAM	equ	$30		; Select 8344 Data RAM
RIC_DRAM_RUN	equ	$34		; Select 8344 Data RAM and do not stop 8344
RIC_IMEM	equ	$31		; Select 8344 Instruction memory
RIC_PC_LO	equ	$32		; Select 8344 Program Counter low byte
RIC_PC_HI	equ	$33		; Select 8344 Program Counter high byte

;
; - BCP test states
;

bcpIDLE		equ	$00		; BCP test not started
bcpRUNNING	equ	$01		; BCP test in progress
bcpDONE		equ	$02		; BCP test completed

;
; - BCP Tests entry points, low bytes
;

BT_POR		equ	$20		; 8344 POR Test starts at 0020


;
; - BCP test error bits
;

bcpRegErr	equ	$01		; BCP register test failed
bcpLoopErr	equ	$02		; BCP loop back test failed
bcpRamErr	equ	$10		; BCP data RAM test failed
bcpError	equ	bcpRegErr + bcpLoopErr + bcpRamErr

;
; Misc.
;

BCP_IM_SIZE	equ	$800		; size of bcp instruction memory (I.M.)
bcp_rdback	equ	$0001000	; start location to store readback from 8344 I.M.
WaitBCPDone	equ	$00020000	; loop count waiting for 8344 to finish testing

		
VendID			equ $5a6f	;unofficial Zorro Vendor ID

;-----------  sResource Directory stuff	;<Id OF>
sRsrc_Board		EQU	1	;Board sResource
CommBoardId		EQU	$A	;Officially defined by Developer Technical Support
ROMRevLevel		equ	1	;ROM revision level (now A) must be < 9



sRsrc_CPU		EQU 128		;identify CPU & memory resources
sRsrc_Comm1		EQU 129		;comm type 1
sRsrc_Comm2		EQU 130		;comm type 2
sRsrc_Comm3		EQU 131		;comm type 3
sRsrc_Comm4		EQU 132		;comm type 4
sRsrc_sMemory		EQU 140		;2nd leved sResource (not seen directly by slot manager)

CatsMemory		EQU 150		;not defined by DTS, 2nd level sRrsource
MinorRAMAddr		EQU 128
MinorROMAddr		EQU 130
MinorDeviceAddr		EQU 132


CatCPU           EQU    $000A  ;
Typ68000         EQU    $0001  ;
DrSwNotThere     EQU    $FFFF  ;Apple MCP has 68K, no on-board driver
DrHwAMCP         EQU    $0001  ;First generation Apple MCP cards

CatCommunication EQU    $0006  ;mb  CatInterface?
Typ3270          EQU    $0013  ;vanilla 3270 for Zorro card 8/23/88
;DrSwNotThere    EQU    $FFFF  ;Apple MCP has 68K, no on-board driver
;DrHwAMCP        EQU    $0001  ;First generation Apple MCP cards

;CatCommunication EQU    $0006  ;mb  CatInterface?
;Typ3270         EQU    $0013  ;vanilla 3270 for Zorro card 8/23/88
;DrSwNotThere    EQU    $FFFF  ;Apple MCP has 68K, no on-board driver
DrHwA3270_5250   EQU    $0006  ;Apple 3270/5250 NB card (Zorro)-implies 8344 chip

;CatCommunication EQU    $0006  ;mb  CatInterface?
Typ5250    	 EQU    $000A  ;5250 protocol (actual DTS constant is Typ32705250)
;DrSwNotThere    EQU    $FFFF  ;Apple MCP has 68K, no on-board driver
;DrHwAMCP        EQU    $0001  ;First generation Apple MCP cards

;CatCommunication EQU    $0006  ;mb  CatInterface?
;Typ5250    	 EQU    $000A  ;5250 protocol (actual DTS constant is Typ32705250)
;DrSwNotThere    EQU    $FFFF  ;Apple MCP has 68K, no on-board driver
;DrHwA3270_5250  EQU    $0006  ;Apple 3270/5250 NB card (Zorro)-implies 8344 chip