Rich Page 6/29/85 Yideo/Sound Timing Gate Array: VIG The VTG implements the horizontal and power supply sync signals, the sound clock, the system timer and the interfaces for the front desk bus modem and the clock chip. The horizontal and power supply sync signals are derived from the video dot rate clock divided by 32 (ie. 2.1888 MHz) using a six bit counter and write registers 10 thru 13 which provide control of the horizontal period, horizontal blank stop, horizontal sync start and horizontal sync stop. The default at reset provides a horizontal rate of 1!l.75KHz and a power supply sync at twice the horizo~tal period at 99.5KHz. The refresh/sound counter is fixed at four times the sound rate using a divide of 41.5 from the 3.6864 Mhz clock which yields a clock of 88.8 KHz. The system timer is a, 16 bit counter which counts at a rate of one fourth of the 3.6864 Mhz clock (ie. approximately once every microsecond). The timer counts upwards to zero. When the timer rolls over to zero, a time out interrupt is generated (ie. s,ets ~ROJ and the system timer is loaded from the the system timer latch (write registers 6 and 7). The front desk bus (FOB) interface is a five line interface which is controlled by write register 4. The five signals are STO, ST1, FS7 (data), FC (clock) and FINT. The, FOB shift register is located at register 2. --===-;z The real time clock (RTC) interface is a four line interface which is controlled by write register 5. The four signals are CINT (1 sec interrupt), RC (clock), CE (clock enable) and RS7 (data). The VTG is located at $FFFOOP0~ with a register spacing of $10. There are six read registers and ten write registers implemented as follows: Bead Register 0: Status $FFFOOOO 0 Bit 0 SRO Status Reg 0, set by the RTC one second interrupt. Bit 1 SR1 ( Status Reg 1, set by the System Timer timeout. Bit 2 FINT . FOB Interrupt input. Bit 3 RSIN RTC serial data input. Bit 4 RA3 VTG Register Address bit 3 .. Bit 5 ES:E Enable ENC pin as sound counter enable. Bit 6 ErA Enable output buffer to RTC if set Bit 7 S10 Set if er~her SRO orSR1 is set. J ..- 17.-"\ Bead Register 2: FDa Shifter Beacf Begister 4: Number..LQw po~ $FFFk 1..0 This register allows the FOB shift register to be read. $FFF~O This register allows the low byte of the number register to be read. Numberliigb $FFFdbso tou"S1J This register allows the high byte of the number register to be read. Bead Register 5: Read Register 6: Timer L~ $FFFD060 \?60 &0 This register allows the low byte of the sy~~em timer to be read.J7'~ Bead Register 7: Timer Hlgh $FFFD070 bClO 1 0 This register allows the high byte of the system timer to be read V , Write Register 0; Bit 0 SRO , Bit 1 SR1 Bit 4 RA3 Bit5 ~ Status $FFFDOOOO RTC one second interrupt bit. System Timer timeout bit. VTG Register Address bit 3. Enable ENe pin as Sound Counter Enable. Note: This register must be initialized at system reset. The remaining bits should be zero when written. $FFFOcfuO wit…

Big Mac MMUSpeclflcation Introduction: The Big Mac MMU is a memory management unit intended for use with the Motorola MC68020. The MMU features a 64 entry, fully associative cache that maps 4096 byte pages from the logical address bus of the MC68020 to the physical address bus of main memory. This allows a logical (virtual) memory space of 4 Gbytes; a maximum physical memory space of 16 Mbytes and a 256 Kbyte user working set. The MMU operates on the upper 20 bits of the logical address yielding the upper 12 bits of the phyical address. The lower 12 bits of the logical address bus are passed straight through to the physical address bus. 68020 CPU BERR 32 bit logical address 12 bit page offset 20 bit logical page address ....- -..........- - - - - - - -... 12 bit physical. page address BERR 24 bit physical address Main Membry 1 Big Mac MMU Specification May 15,1985 If the upper 20 bits of the logical address are contained in any of the 64 entries in the MMU, the upper 12 bits of the physical address are provided within 65ns. This permits the MMU to function without wait states. If the page Is resident In the MMU. the access control bits associated with that page are also checked to see H write protection and or execute only protection is in effect. If the upper 20 bits of the logical address are DQ1 contained in any of the 64 entries in the MMU, a Bus Error (BERR) signal will be asserted. This will suspend the execution of the instruction that caused the "miss", and system software can then load the MMU with the correct physical address of the page that caused the miss. The suspended instruction can then be restarted. If the logical address is contained in the MMU and a write protection or execute only protection violation is detected, a Bus Error is also generated. Ten 16 bit status registers are implemented within the MMU to allow access to the following information: Page Accessed (status registers 0 through 3 for use in generating LRU info), Page Dirty (status registers 4 through 7), Exception Cause and MMU mode (status register 8) and Logical Address Latch (status register 9). Operation: Supervisor and user states are defined by the function code 2 bit (FC2) of the CPU (with FC2-=1 --> supervisor and FC2-=O _..> user). The CPU and MMU combination operate with Supervisor state addresses always unmapped. User state can operate either mapped (by clearing the MODE bit in status register 8), or unmapped. The unmapped state is entered by setting the MODE bit in register 8. In the unmapped state the MMU presents logical address bits LA23 through LA 12 directly to the physical address bits PA23 through PA12. Independent of the mapping of User state, the registers of the MMU are accessible for reading or writing ~ from Supervisor state. The registers LARO through LAR63 (located at byte offsets $00000 through $3FOOO) contain the logical addresses of the 64 pages to be mapped into the physical pages. The registers PARO through PAR63 (located at…

Rich Page 6/10/85 BIG MAC DATA SHEET The Big Mac is a high performance Macintosh whic.h can be used as both a Macintosh and as a work station. It is implemented using three 500 gate bipolar ~Jate arrays and one 1200 gate cmos gate array. Display: 1024 x 800 8IW display, 60 Hz refresh, 70Mhz dot rate CPU: 68020 with option for 12M, 16M, and IBM clock rate FPU: 68881 as floating point !coprocessor NIJIU: Custom M~I1U with 4Gb ,address space, 64 entry TLB with 4Kb pages which offers a working set size of 256Kb. Virtual address space is configurable from 16M to 4Gb. The MMU~ supports write and execute protection and <{/ V'iJ;,-u_~ ~ 6 dirty bits for ea-ch-page. - ~"~----./ U . ,c-- I Memory: 2 Mb of DRAM on main logic board using 256Kx1 Separate video memory using 64Kx4 256Kb of ROM using two 1M parts RAM is limited to 10Mb max DMA: 68450 (use 68440 if no 2nd SCC) with support to access the full 32 bit address space. 1/0: Two see chips (ie. four serial ports) SCSI port for internal 20Mb hard disk and external devices Double sided SONY, IWM chip interface, option for 2nd SONY Macintosh compatible sound with SONY sound chip. Front Desk Bus for keyboard, mouse, etc. Real Time ()Iock with battery backup Soft power on/off. Slots: Four 1/0 Slots with access to 32 bit address and data bus Two Memory Expansion Slots Rich Poge 61G MAC LOGIC BLOCK DIAGRAM 6/2/85 68440 CPU DMA 68020 OR 68450 1\1-1\4 FPU FOUR I/O SLOTS 68881 GATE ARRAV-3 SOUND &. VIDEO TIMING 0, 031-D24 ROM'256Kb GATE ARRAV-1A NUX 16 TO 8 VIDEO COUNTER SCC IWM SCSI CLOCK FRONT DESK MMU WITH 64 ENTRV TLB VIDEO RAM (8 - 64Kx4) , GATE ARRAV-1B NUX 1B TO 9 SND COUNTER . . CSC :F109 :F161 70M CPU 7.8M -_ MODE = 1 ~---.. .... GATE ARRAV-4 NUX 20 TO 10 SND COUNTER 35M GATE ARRAV-2 CLOCK GENERATOR MAIN RAM EXPANSION RAM (32 - :>56KxO (32 - 1Mx1)

Rich Page 8/14/85 APPLE CONFIDENTIAL Programmers Model for the Big Mac Introduction This document describes the Big Mac hardware from the programmers view of the machine which includes a description of the address space maps and a description of each device. The CPU clock is generated by the clock generator gate array which is controlled by three signals CSELO, CSEL 1 and M70. These signals are controlled by dip switches and described by the following table. x" ~ELQ \.~ ~ ,~ / rr} O~ ~EL1 MIQ ~FREQ ®a...CCK 0 1 0 1 0 0 1 1 0 0 0 0 66.3552Mhz 66.3552Mhz 66.3552Mhz 66.3552Mhz 11.0592Mhz 14.7456Mhz 16.5888Mhz 22.1184Mhz 0 1 0 1 0 0 1 1 1 1 1 1 70.0416Mhz 70.0416Mhz 70.0416Mhz 70.0416Mhz 11.6736Mhz 15.5648Mhz 17.5104Mhz 23.3472Mhz CACHE:50PE# lnterrupts Level# Interrupt source 1 2 3 4 5 Power sW'itch DMA IRQ and Sound interrupt SCSI IRQ VIA IRQ (timer, vsync and onesec) Reserved for slot interrupts SCCIRO NMI SVJitc 6 7 l , , - ( L DC \l.- -_. -~"-- .. __ ."- '/~\CPlA. C.LD( Rich Poge 8/14/85 Big Moe Address Spoce Mop (Supervisor Stet e) --. - ~ XXF9000 0 XXEOOOOO XXDOOOOO XXCOOOo"O I/O SLOTS XXAOOOOO XX900000 XX800000 XX700000 XX600000 XX500000 XX400000 XX300000 XX200000 XX100000 XXOOOOOO XXFEOOOO XXFDOOOO MMU ROM high i XXBOOOOO XXFFOOOO reserved (" ""\ xx~pooo XXFBOOOO XXFAOOOO XXF90000 reserved ---,-"-- DMA VTG ---- IWM VIA SCC RAM RAM RAM RAM RAM or ROM low RAM RAM RAM RAM or ROM zero XXFOOOOO --'-.--- SCSI SCREEN RAM -- reserved ---- Rich Poge 8/14/85 Big Moe Address Spoce Mnp (User stote) r I/O Frrooooo FFFFOOOO FFEOOOOO DMA MMU (no 6ccess) FFCOOOOO ROM high - VIA FFFBOOOO reserved FFBOOOOO ...,,-----.-.--- - FFF90000 SCC ,----==--- SCSI _. - SCREEN FF AOOODO FFFOOOOO L I I 0070000 0 - RAM _. RAM 00600000 - RAM 00500000 RAM or ROM low 00400000 0030000'0 -, IWM FFFCOOOO FFFAOOOO -, VTG FFFDOOOO FFDOOOOO reserved I- FFFEOOOO SLOTS - RAM I- 00200000 00100000 00000000 I - RAM RAM RAM or ROM zero ...J reserved - cpu (continued) Bus Error A bus error can be generated by either the AS watchdog or the MMU. The AS watchdog will generate a bus error for bus cycles longer than 2us. Hjgh Decode Map Register There exists a 4 bit register (located on the VIA) which controls the position of the ROM and provides a mechanism to limit the number of address bits used for decoding logical addresses. This register can \~~ programmed to cause the high address bits (those above A23) to be significant to the decoding hardware. This allows a range of address space sizes from 24 to 32 bits. In the smallest configuration, the address space is limited to 16Mb and the upper eight bits are insignificant to decoding which will allow software to use the upper eight bits as tags. In the largest configuration, the address space is 4Gb and none of upper bits are available. Address Space Map The address space map is determined by the High Decode Map reg…

Rich Page 6/29/85 Programmers Model for the Big Mac Introduction This document describes the Big Mac from the programmers view of the machine which includes a description of the address space map, the system registers and the decoding of the I/O devices and their registers. The Big Mac MMU and decoding logic maps the 32 bit address space of the 68020 into two address spaces, one for RAM and the other for Screen, ROM and I/O. There exists a 5 bit register named the High Decode Map register which controls the position of the ROM and provides a mechanism to limit the number of address bits used for decoding logical addresses. The HOM register can'$rogrammed to cause the high address bits (those above A23) to be significant to the decoding hardware. This allows a range of address space sizes from 24 to 32 bits. In the smallest configuration, the address space is limited to 16Mb and the upper eight bits are insignificant to decoding which will allow software to use the upper eight bits as tags. In the largest configuration, the address space is 4Gb and none of upper bits ~ __--==:::::::::::::==-:-- are available. CJ (. ~:J Address S pace Map <z The address space map is determined by the 5 bit HOM register and the FC2 signal (ie. user/supervisor bit from the 68020). See the following page for drawings of the supervisor and user state address space maps. There are five configurations which are defined as follows: .EQg HOO !-Dy14 tpv15 VMsize RAMsize t>S.LQr RaJ! SCREEN 1 x x x 16Mb 10Mb A23 o 1 1 16Mb -- 8Mb A23 o o ,. 1 '1 32Mb 16Mb A24 *A23 o o o 1 512Mb 256Mb A28* A24 * A23 o o o o I\\~~te: 4Gb ---·2Gb A31 *A28* A24 * A23 The first configuration (ie. FC2 = 1) is supervisor state and the last four configurations (ie . FC2 == 0) are user state. Rich Pege 6/21/85 - Big Moc Address Spoce Map (~upervisor Stcte) r I/O XXFOOOOO SLOTS XXFFOOO XXFEOOO System Regi ster-- ~-l _.- ° ° DMA ~T G.,S NO., RT XXFDOOOO XXDOOOOO XXCOOOOO XXBOOOOO reserved I--~--~ ROM h1gh L----=~--~ re s erv ed r--~--~ , XXFCOOOO XXFBOOOO IWM L.. SCC2 ..... SCC1 XXFAOOOO "-- XXF90000 L....- SCSI SCREEN XX90qOOO XXSOOOOO XX700000 XX60qooO RAM .:sou C.l \'=c> I...-- - ]- -".- -'-..J RAM I---'--~ RAM I----~ RAM RAM )()(SOO,OOO I---'-~ XX40QPOO RAM or ROM! low I--=~~~ XX300POO I---'-~ RAM RAM RAM )()(OOOOOO MMU XFOOOOO I~ \ .c., F.D.B _I\fi RAM or ROM zero -.....,/.---~~~- - : ~ -~~~ Q<~~~~ -- / R1Ch Page 6/21/85 Big M8C Address Sp8ce M8P (User State) .,......... FFFOOOOO FFEOOOOO FFDOOOOO FFCOOOOO FFBOOOOO FFAOOOOO . I/O SLOTS FFFFOOOO FFFEOOOO FFFDOOOO reserved ROM high reserved FFFCOOOO FFFBOOOO FFFAOOOO FFF90000 00600000 00500000 00400000 00300000 00200000 00100000 00000000 DMA VTG,SND ,RTC,FDB IWM SCC2 SCCl SCSI ._---,- SCREEN FFFOOOOO 00700000 System Regi ster RAM RAM RAM RAM or ROM low RAM RAM RAM RAM or ROM zero MMU -- Note: The bi ts HDM3, HDM4 and HDM5 define t…

Now that we have a goal in sight (bringing up BigMac in timely fashion), I thought we should formalize and agree on how we are to reach this goal. I see it as a four stage process. First is of course, the delivery of the breadboard machine on or about 8/15 to the software group. Second stage is to get some kind of debugging environment in the machine. Third is to download our version of The ROM into ram and get as much of it working as we can andlor as is necessary to boot. The last stage is to get the machine to boot up and hopefully run an application. I propose that we try to use the MacDB debugger from the MDS system. This debugger uses a Mac as a very intelligent terminal talking to a small monitor «1k bytes) in the target machine. This is a very powerful debugging system that is for the most part done and should require little to port to BigMac. The one thing that it lacks is the ability to disassemble 68020 code (ho'lVever I have a line on a possible updated version) but I don't see that as much of a problem as very little 68020 specific code is in the system. I have the sources to the monitor (Macl'~ub) and the debugger (MacDB) so that we can modify them as nee.d be. Tom will be providing a ROM image for BigMac to be downloaded and debugged. Rodger has been working on a debugger/downloader that we can modify to use the MacDB protocol for downloading the ROM image. Once the image is in RAM we can debug the initialization parts leading up to booting the disk. From my discussions with Tom and Rodger last week it was decided that we would boot from the hard disk. This is a win for two reasons. First it greatly simplifies the boot process by not having to get wrapped up in the Sony driver (and EEEK!, the IWM) and second it is too cool for words to boot from the hard disk. First pass is will be getting the Finder to run. With some luck their might be time to get Paint or Write to work. So much for my view of the world. Please let me know if you see any problems in this strategy or perhaps we can discuss it at the next BigMac meeting. team: Rodger Mohme Peter Ashkin Tom Saulpaugh Rich Page from: Mike Hanlon