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Monitor Notes.Txt

Monitor Notes.Txt

Lisa · TXT
FilenameMonitor_notes.txt
Size0.02 MB
Subsection pascal_monitor
Downloads2
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Contents
.PAGE

;---
;				ZERO PAGE MAPPING
;
;	The following equates are for dividing RAM into logical areas;
;	however, as the code grew, this convention was not strictly adhered
;	to and therefore one will find both "LOCAL" and "GLOBAL" variables
;	scattered throughout the RAM area
;+++

IOB	.Equ 00	;  INPUT OUTPUT BLOCK
	This starts at $FCC000.  All ofsets from here are WORD offsets!!!.  For example, COMMAND is
	at FCC002 (offset of one word).  Actually, only the low byte of the word has any
	significance.

SHARERAM	.Equ 10	;  READ/WRITE SHARED RAM, INITIALIZED BY 6504 ON BOOT
	Starts at $FCC020

STATUS	.Equ 20	;  READ ONLY STATUS FROM THE 6504
	$FCC040

IIOB	.Equ 30	;  INTERNAL IOB
	$FCC060  This can be used to check the last command excuted
GLOBALS	.Equ 40	;  6504 INTERNAL GLOBALS
	$FCC080  This is where the actual "ROM" is maintained.  Of course these can be changed, but
	don't even think about it

LOCALS	.Equ 68	;  LOCAL VARIABLES
	$FCC0D0  Local storage mainly.  Probably should not be changed

;;	THESE APPEAR, FROM THE LISTING PROVIDED, TO BE HEX NUMBERS UNLESS FOLLOWED BY A DECIMAL
;;	1/6/89 ARS

.PAGE

;---
;
;				IOB
;
;  THE IOB IS ALWAYS COPIED INTO THE INTERNAL IOB (IIOB) AREA BEFORE USAGE
;  SO THAT THE 68K CAN START TO BUILD A NEW COMMAND INTO THE IOB AS SOON AS
;  POSSIBLE.  ALL REFERENMCES TO THE IOB OF IIOB ARE DONE IN THE FOLLOWING
;  FORMAT:
;	IOB	IIOB
;	--------	--------
;  GOBYTE	IOB+GOBYTE	IIOB+GOBYTE
;  DRIVE	IOB+DRIVE	IIOB+DRIVE
;
;+++
IOBSIZE	.Equ 07	;  SIZE OF IOB BLOCK USED FOR PARAMETER PASSING
GOBYTE	.Equ 00	;  COMMAND BYTE FROM 68K
	$FCC000/060
;	00	COMMAND ACCEPTED BY THE 6504, 68K MAY ISSUE A NEW COMMAND
;	80-89	COMMAND FROM 68K TO 6504
;	80	NULL, TESTS HANDSHAKE
;	81	RWTS COMMAND, COMMAND CODE IN 'COMMAND'
;	83	SEEK
;	84	CALL ADDRESS IN 6504
;	85	CLEAR STATUS
;	86	SET MASK
;	87	CLEAR MASK
;	88	WAIT IN ROM
;	89	Go jump to self forever (Their case change ARS)
;
;	01-7F,82,90-FF		*** RESERVED ***

COMMAND	.Equ 01	;  RWTS COMMAND CODE
	$FCC002/062
;	00	READ	Read Read the Data @ Drive/Side/Track/Sector
;	01	WRITE	Write Read the Data @ Drive/Side/Track/Sector
;	02	UNCLAMP	Unclamp the disk in Drive
;	03	FORMAT	Format the disk in Drive
;	04	VERIFY	Verify the disk in Drive
;	05	FORMAT TRACK	Format single Track on the disk in Drive
;	06	VERIFY TRACK	Verify single Track on the disk in Drive
;	07	READBF	Read w/o checksum verification
;	08	WRITEBF	Write w/o checksum creation
;	09	CLAMP	Clamp the disk in Drive
;	0A-FF		*** RESERVED ***

MASK	.Equ COMMAND	;  MASK FOR SETTING AND RESETTING IMSK & IST
	$FCC002/062
;	08	SET OR CLEAR INTERRUPT MASK FOR UPPER DRIVE
;	80	SET OR CLEAR INTERRUPT MASK FOR LOWER DRIVE
;	01	CLEAR DISK INSERTED INTERRUPT FOR UPPER DRIVE
;	10	CLEAR DISK INSERTED INTERRUPT FOR LOWER DRIVE
;	02	CLEAR BUTTOM PRESSED INTERRUPT FOR UPPER DRIVE
;	20	CLEAR BUTTOM PRESSED INTERRUPT FOR LOWER DRIVE
;	04	CLEAR R/W COMMAND COMPLETED INTERRUPT FOR UPPER DRIVE
;	40	CLEAR R/W COMMAND COMPLETED INTERRUPT FOR LOWER DRIVE

ADRL	.Equ COMMAND	;  LOW BYTE OF ADDRESS FOR 6504 CALL
	$FCC002/062
ADRH	.Equ ADRL+1	;  HIGH BYTE OF ADDRESS FOR 6504 CALL
	$FCC004/064
		;  A call to "1FFB" will reset the 65404

DRIVE	.Equ 02	;  DRIVE NUMBER
	$FCC004/064
;	00	DRIVE 0 UPPER DRIVE
;	80	DRIVE 80	LOWER DRIVE

SIDE	.Equ 03	;  SIDE NUMBER
	$FCC006/066
;	00	SIDE 0 UPPER SIDE OF MEDIA
;	01	SIDE 1 LOWER SIDE OF MEDIA

SECTOR	.Equ 04	; SECTOR NUMBER
	$FCC008/068
;	00-15	MAXIMUM DEPENDES ON TRACK NUMBER

TRACK	.Equ 05	;  TRACK NUMBER
	$FCC00A/06A
;	00-2D	46 TRACKS TOTAL		(twiggy, Sony has 80 -- 0-79)

SPEED	.Equ 06	;  SPEED OVERRIDE
	$FCC00C/06C
;	00	NOOVERRIDE, SPEED IN DEPENDING ON TRACK NUMBER
;	01-FF	Modifier value added to nominal speed

FMTCNFN	.Equ 07	;  Format configuration byte
	$FCC00E/06E	;  Used to ensure format is not executed by mistake
;	FF	FMTCNFM must be = FF for foramt/format track to work

ERRSTAT	.Equ 08	;  ERROR STATUS, RETURNED AFTER R/W COMMANDS
	$FCC010/070	;  See constants for current error code values
	This also seems to be used for address mark storage?

DISKID	.Equ 09	; Current id of the disk last accessed
	$FCC012/072
;	00	UIniFile/DuoFile disk
;	01	Lisa disk
;	02	Macintosh disk

NoSides	.Equ 0A	;  Number of sides of disk drive mechanism
	$FCC014/074

DrvError	.Equ 0B	;  Hard errors get returned throught his byte
	$FCC016/076

HostSeek	.Equ 0C	;  When moving the head this location = 'FF'
	$FCC018/078

SeekErr	.Equ 0D	;  When seek does not handshake then = '0F'
	$FCC01A/07a
	
.Page

;--
;			Shared RAM
;
;  SHARED RAM COMES IN TWO FLAVOERS:  'READ/WRITE' AND 'READ ONLY'.  THE 68K CAN,
;  OF COURSE, READ AND WRITE TO ANY BYTE IN THE RAM AT ANY TIME BUT THIS IS NOT
;  VERY WISE, (ONE MIGHT SAY VERY FOOLISH...), SO THE BY 'READ ONLY' WE MEAN
;  MEMORY THAT NEVER SHOULD BE WRITTEN TO BY THE 68K BUT IS VALID TO READ AT
;  ANY TIME.  TYPICAL 'READ ONY' VARIABLES ARE THE STATUS FLAGS CLMED0 AND
;  CLMPED80 THAT TELLS THE 68K THAT A DISK IS CLAMPED IN DRIVE 0 OR 80
;
;  'READ/WRITE' SHARED MEMORY IS, FOR EXAMPLE, THE IOB BUT IN THIS CASE IT IS
;  A FAMILY OF 'CONSTANTS' SET UP ON COLD START BY THE 6504 TO THEIR DEFAULT
;  VALUES, BUT THEY CAN BE CHANGED AT ANY TIME BY THE 68K TO ANY VALUE.  THERE
;  IS NO CHECKING OF THE RANGE OF THESE VALUES O THE NEW ONE BETTER MAKE SENSE
;  OR THE 6504 MIGHT GO OF TO NEVER, NEVER LAND...
;
;		SHARED:  READ/WRITE
;++

MSpdTbl	.Equ ShareRam
	$FCC020

SCDLY	.Equ SHARERAM+5.	;  Speed change delay in 5 ms intervals
	$FCC02A

HEADELAY	.Equ SHARERAM+6.	;  Head settling time in 5 ms intervals
	$FCC02C

MAXDDLY	.Equ SHARERAM+7.	;  Timer value in 2/3 second before motor off
	$FCC02E

ROMIDNUM	.Equ SHARERAM+8.	;  ROM identification number ( 0018/FCC031 )
	$FCC030

MAXRETRY	.Equ SHARERAM+9.	;  Maximum number of retries during a read/rwite
	$FCC032

MAXRECAL	.Equ SHARERAM+10.	;  Maximum number of recalibrations during a r/w
	$FCC034

StpDly	.Equ SHARERAM+11.	;  Step dely time in 100 usec intervals
	$FCC036

MONDLY	.Equ SHARERAM+12.	;  Motor on delay time in 5 ms intervals
	$FCC038

.Page

;++
;		SHARED:  READ ONLY
;--

Clamped	.Equ Status	;  Disk in Place (=0 EMPYT, =FF CLAMPED)
	$FCC040
MtrOn	.Equ Clamped+1	;  DRIVE MOTOR SELECT (0=OFF, FF=ON)
	$FCC042

CurTrack	.Equ Status+2	;  value of current track
	$FCC044
CurClass	.Equ CurTrack+1	;  Current track class (0:  4)
	$FCC046

DrvConn	.Equ Status+4	;  Will be 'FF' if a drive is physically there
	$FCC048
FmtType	.Equ DrvConn+1	;  '2' for single, '22' for double sided mechanism connected
	$FCC04A

RetryCnt	.Equ Status+6	;  RETRY COUNT
	$FCC04C

RecalCnt	.Equ RetryCnt+1	;  RECALIBRATION COUNT
	$FCC04E

ImAlive	.Equ Status+8	; THIS VARIABLE SPINNS AS LONG AS THE MAIN LOOP IS EXECUTING
	$FCC050

Counter	.Equ Status+9.	;  GENERAL COUNTER
	$FCC052

HoldInx	.Equ Counter+1	;  Holds command index temporarily
	$FCC054
FmtGap	.Equ Counter+2	;  Amt * 5 of 20 usec 'FF's to write as selfsync
	$FCC056
Imsk	.Equ Status+12.	;  Bits 7 & 3 are mask; if set the drive enabled
	$FCC058
DipIntr	.Equ Imsk+1	;  Flag reflects DIP interrupt
	$FCC05A
OkToGo	.Equ Imsk+2	;  REFLECTS FDIR (=0, FDIRL; <>0, FDIRH)
	$FCC05C
IST	.Equ Imsk+3	;  INTERRUPT STATUS
	$FCC05E

;	Bits of IST are numbered for LSb (0) to MSb (7)
;
;	Bit	Meaning
;	---	-------
;	0	Drive 0 disk inserted
;	1	Drive 0 button pressed
;	2	Drive 0 R/W completed
;	3	Logical OR of bit 0,1 & 2
;	4	Drive 80 disk inserted
;	5	Drive 80 button pressed
;	6	Drive 80 R/W completed
;	7	Logical OR of bit 4,5 & 6

AdrMk1	.Equ	IIob+8	;  5 values that indicate start and end of address field
	$FCC050
AdrMk2	.Equ	AdrMk1+1	These seem to be overlapping w/ some of the good stuff in
	$FCC052		the main IIob?  Maybe the two purposes are mutualy exclusive.
AdrMk3	.Equ	AdrMk1+2
	$FCC054
AdrMk4	.Equ	AdrMk1+3
	$FCC056
AdrMk5	.Equ	AdrMk1+4
	$FCC058

.Page
		; Following 3 byte counter controls both testing
		; for DIP and shutting off teh motors.  When
WtLow	.Equ Globals	; the low 2 bytes = 0 then test for DIP. When
WtMid	.Equ WtLow+1	; the third byte becomes 0 the heads are parked
WtHih	.Equ WTLow+2	; and the motors are turned off
	$FCC080/082/084
		; For timing and space purposes during writing
		; of data, an indexed by "y" through zero
INXPTRL	.Equ Globals+3	; pge instruction is used.  The two bytes
INXPTRH	.Equ INXPTRL+1	; hold the base address for the index.
	$FCC086/088

		; Some constants for timing purposes
K000	.Equ Globals+5	; A constant '00'
K0FF	.Equ K000+1	; A constant 'FF'
	$FCC08A/08C

		; Following 8 locations hold error counters for
		; various read errors.  The first three are for
		; error w/ reading data and the last five are
		; for errors associated w/ the header.
STSLP	.Equ GLOBALS+8.	; Read Data Starting Bitslip
	$FCC090
BSCNT	.Equ StSlp+1	; Read Data ending Bitslip
	$FCC092
CSERROR	.Equ StSlp+2	; Read data Checksum error
	$FCC094
RASTRT	.Equ StSlp+3	; Read Address Starting Bitslip
	$FCC096
RAEND	.Equ StSlp+4	; Read Address Ending Bitslip
	$FCC098
RASCTR	.Equ StSlp+5	; Read Address wrong sector
	$FCC09A
RATRK	.Equ StSlp+6	; Read Address wrong track
	$FCC09C
RACSUM	.Equ StSlp+7	; Read Address Checksum error
	$FCC09E
ERRLEN	.Equ 7	; 8 bytes, zero based

CSMFND	.Equ Globals+16.	; CHECKSUM read from disk
	$FCC0A0
VOLFND	.Equ CsmFnd+1		; 0 = UniFile/DuoFile, 1 = Lisa, 2 = Mac
	$FCC0A2
SDFND	.Equ CsmFnd+2		; SIDE FOUND
	$FCC0A4
SECFND	.Equ CsmFnd+3		; SECTOR FOUND
	$FCC0A6
TRKFND	.Equ CsmFnd+4		; TRACK FOUND
	$FCC0A8
CSUM	.Equ CsmFnd+5		; Checksum calculated from ADDRESS data
	$FCC0AA
ADRSLEN	.Equ 4		; LENGTH OF ADDRESS HEADER - 1

TrkFlg	.Equ Globals+22.
	$FCC0AC
MtrFlg	.Equ TrkFlg+1
	$FCC0AE
StpAmt	.Equ TrkFlg+2
	$FCC0B0
Direct	.Equ TrkFlg+3
	$FCC0B2

IndexL	.Equ Globals+26.
	$FCC0B4
IndexH	.Equ IndexL+1
	$FCC0B6
RangeL	.Equ IndexL+2
	$FCC0B8
RangeH	.Equ IndexL+3
	$FCC0BA

CPBY01	.Equ Globals+30.	; Composite byte formed from BUFFER[ 2FF:301 ]
	$FCC0BC
CPBY02	.EQY CPBY01+1		; [ 3FE:3FF ]
	$FCC0BE
CPCKSUM	.Equ Globals+32.	; Composite byte formed from 3 checksum bytes
	$FCC0C0
CKSUM1	.Equ CPCKSUM+1		; First checksum byte
	$FCC0C2
CKSUM2	.Equ CPCKSUM+2		; Second shecksum byte
	$FCC0C4
CKSUM3	.Equ CPCKSUM+3		; Third checksum byte
	$FCC0C6

TCKSM1	.Equ Globals+36.	; During a read of data, the checksum is read
	$FCC0C8
TCKSM2	.Equ TCKSM1+1		; into "CKSM1..3".  A new checksum is created
	$FCC0CA
TCKSM3	.Equ TCKSM1+2		; and stored in these 3 bytes to verify matters
	$FCC0CC
TEMPSEC	.Equ Globals+39.	; TEMPRARY SECTOR COUNTER USED BY FORMAT
	$FCC0CE

.Page

;--
;			LOCAL VARIABLES USED IN ONE OR SEVERAL ROUTINES
;++

RWCSMFLG	.Equ LOCALS		; Flag fro usage of host supplied checksum
DELAY	.Equ LOCALS+1		; COMPUTED DELAY FOR TOTAL SEEK

Sv1	.Equ LOCALS+2		; storage during Write16
Sv2	.Equ Sv1+1
Sv3	.Equ Sv1+2
Sv4	.Equ Sv1+3

TEMP1	.Equ Locals+6.		; 2 Locations for temporary by many routines
TEMP2	.Equ TEMP1+1

DatMk1	.Equ Locals+8		; 5 values that indicate start and end of Data field
DatMk2	.Equ DatMk1+1
DatMk3	.Equ DatMk1+2
DatMk4	.Equ DatMk1+3
DatMk5	.Equ DatMk1+4

LOWCNT	.Equ LOCALS+13.		; Holds value for physiacl interleave count
HIHCNT	.Equ LOWCNT+1.		; Same but opposite/complimentary value
CNTPTR	.Equ LOWCNT+2.		; Pointer to which cnt to use ( high or low )
TOTCNT	.Equ LOWCNT+3.		; Total count of sectors written

TEMP3	.Equ Locals+17.
TEMP4	.Equ TEMP3+1

RtyFlg	.Equ Locals+19.		; flag for use in BadAddr error handling
Uu6	.Equ Locals+20.		; 2 unused locations

Cmdx	.Equ Locals+21.
SaveL	.Equ Locals+22.
SaveH	.Equ Locals+23.
CmdLeng	.Equ 3F		; 64 byte ring buffer of 8 byte IOB's
SavIndex	.Equ 80

; *** NOTE -- Ram from 'C0' to 'FF' is used by the 68K as parameter memory ***

LSTUSED	.Equ 0BF		; last used location in the ZERO PARE RAM

.Page
;--
;
;			CONSTANTS
;
;++

BUFR12SZ	.Equ 0B		; LENGTH OF 12 BYTE BLOCK HEADER - 1
NIBLRETR	.Equ 20		; THE NUMBER OF NIBBLES READ SEARCHING FOR THE
			; FIRST ADDRESS MARK DURING A READ
MAXTRACK	.Equ 4F		; MAXIMUM TRACK NUMBER: 79.
MINTRACK	.Equ 0		; MIMIMUM TRACK NUMBER: 0
MAXCLASS	.Equ 04		; Maximum track class value -- range from 0..4
MINSECNT	.Equ 08		; Minimum sector count
MAXSECNT	.Equ 0C		; Maximum sector count
MINSPEED	.Equ 0D4		; Minimum speed value
MAXSPEED	.Equ 038		; Maximum speed value -- Low # = high speed
OkDly	.Equ 28.

CNFMVAL	.Equ 0FF		; Format configuration check byte
LOW6	.Equ 3F		; mask for low 6 bit

MaxCmd	.Equ 09		; 10 commands return FDirH ( -1 )
CmdNumb	.Equ 07		; Seven commands nao accessed through '81'
NullCmd	.Equ 080		; Null/Handshake command
RwtsCmd	.Equ 091		; Read/Write Track/Sector command value
LwCmdNo	.Equ 083		; Lowest command number ( not including '81' )
ClStsCmd	.Equ 085		; Command to clear interrupt status
WrtCmd	.Equ 01		; Value of command to write data to disk
WrtBfCmd	.Equ 08		; Write data, brute force method
FrmtDsk	.Equ 03		; Value of command host to to format disk
VrfyDsk	.Equ 04		; Value of command host to to verify disk
FrmtTrk	.Equ 05		; Value of command from host to format a track
VrfyTrk	.Equ 06		; Value opf command from host to verify a track

ADM1	.Equ 0D5		; Address mark one
ADM2	.Equ 0AA		; Address mark two
ADM3	.Equ 096		; Address mark three
DDM3	.Equ 0AD		; Data mark three

BitSlp1	.Equ 0DE		; Bit slip mark one
BitSlp2	.Equ 0AA		; Bit slip mark two

RclStep	.Equ 4.		; # of steps to take away from Trk00 during recal
OneScc	.Equ 200.		; constant for a one second wait
TmOutRcl	.Equ 100.		; Timeout for recal wait
RdAdrTmt	.Equ 08.		; Tiomeout for looking for address header
IWMMode	.Equ 01F		; constant to setup IWM modes
TurnRound	.Equ 08.		; 5*8=40 msec turn around time for changing directions

Lrge	.Equ 05.
Smal	.Equ 01.
TblJmp	.Equ 09.
WHih	.Equ 17.		; '11' hex
WLow	.Equ 00.
tLow	.Equ 20.

;  ERROR NUMBERS

GErrCmd	.Equ 01		; Gobyte error:  Invalid command
GErrDrv	.Equ 02		; Gobyte error:  Invalid drive number
GErrSid	.Equ 03		; GoByte error:  Invalid side number
GErrSec	.Equ 04		; Gobyte error:  Invalid Sector number
GErrTrk	.Equ 05		; Gobyte error:  Invalid Track number
GErrMsk	.Equ 06		; Gobyte error:  Invalid mask
GErrClm	.Equ 07		; Gobyte error:  No clamped disk in drive
GErrEna	.Equ 08		; Gobyte error:  Drive not enabled
GErrIntr	.Equ 09		; Gobyte error:  Pending interrupts not cleared
GErrFmPr	.Equ 10.		; Gobyte error:  Invalid format parameter

PErrROM	.Equ 11.		; Program error:  ROM test failed
PErrInt	.Equ 12.		; Program error:  Random IRQ, NMI or BRK

DErrCal	.Equ 13.		; Drive error:  time out while looking for track zero
IWMError	.Equ 14.		; Fatal error:  IWM doesn't respond to commands
StepErr	.Equ 15.		; Handshake diod not occur when stepping
DErrTk0	.Equ 16.		; Drive Error:  Unable to leave track zero location

SErrProt	.Equ 20.		; Errstat error:  Write protect error
SErrFrmt	.Equ 21.		; Errstat error:  Can't verify disk
SErrClmp	.Equ 22.		; Errstat error:  Unable to clamp disk
SErrRd	.Equ 23.		; Errstat error:  Read error
SErrWr	.Equ 24.		; Errstat error:  Write error
SErrUclmp	.Equ 25.		; Errstat error:  Unable to unclamp diskette
SErrNoA9	.Equ 26.		; Errstat error:  Cannot find A9's during chkspd
SErrTmt	.Equ 27.		; Errstat error:  Unable to adjust speed w/in timeout
SErrM1Tk	.Equ 28.		; Errstat error:  Cannot write speed track

ErrHdr	.Equ 30.		; UnderRun while writing header
ErrWrt	.Equ 31.		; UnderRun while writing data fields

.Page
;++
;
;		Data Buffer equates and Bad Block equates
;
;--

StackSt	.Equ 0CF		; Init stack to "01CF" -- push down stack
SctrCnt	.Equ 01D0		; During VERIFY, will no. of bad sectors
TrkNumb	.Equ SctrCnt+1		; Track number where bad sector occurred
SidNumb	.Equ SctrCnt+2		; Side number where bad sector occurred
SctrSav	.Equ SctrCnt+3		; Start of buffer where sector numbers are saved

Page01	.Equ 100		; last 12 bytes of data are for read/write
Bufr12	.Equ 1F4		; last 12 bytes of data for raed/write
Page02	.Equ 200		; 256 bytes of data for read/write
Page03	.Equ 300		;  "

Pg2Len	.Equ 0FF		; # of bytes to read during Wrbf02 loop
Pg3Len	.Equ 0FE		; # of bytes to read during Wrbf03 loop

.Page

;--
;		I/O Space
;++

IOSpace	.Equ 800		; name for beginning of I/O space offsets
Off	.Equ 00		; Offset to switch a phase off
On	.Equ 01		; Offset to switch a phase on
Zero	.Equ 00		; Offset to drive zero
Eighty	.Equ 01		; Offset to drive eighty
Low	.Equ 00		; PwmEna + Low enables output of PWMReg
High	.Equ 01
InWard	.Equ 00		; direction offsets
OutWard	.Equ 01

CA0	.Equ IOSpace		; Control signal 0 for MCI PAL in Sony drive
CA1	.Equ IOSpace+2		; signal 1
CA2	.Equ IOSpace+4		; signal 2
LStrb	.Equ IOSpace+6		; Load strobe -- 0 to 1 to 0 will strobe PAL

MtEna	.Equ IOSpace+8		; Enables output of DrvEna

DrEna	.Equ IOSpace+10.	; = 0 --> drive 0, = 1 ==> drive 80

Q6L	.Equ IOSpace+12.	; Low = Read or Write
Q6H	.Equ Q6L+1		; High = Sense or Write Load
Q7L	.Equ IOSpace+14.	; Low disables writing to disk
Q7H	.Equ Q7L+1		; Enables /WrReq output of IWM

CntEna	.Equ IOSpace+16.	; low enables PWM counter/comparator

PwmEna	.Equ IOSpace+22.	; High enables pulses to Sony, else always low

DisL	.Equ IOSpace+24.	; Memory enable for the 68K
DisH	.Equ DisL+1		; Memory disable for the 68K

Side0Sel	.Equ IOSpace+26.	; Selects side 0
Side1Sel	.Equ Side0Sel+1		; Selects side 1

BootL	.Equ IOSpace+28.	; Disk Diag Line; when High then I'm listening
BootH	.Equ BootL+1

FDirL	.Equ IOSpace+30.	; Deselects the interrupts to the 68K
FDirH	.Equ FDirL+1		; Selects the interrupts to the 68K

PWMReg	.Equ IOSpace+32.	; Selects the PWM register for writing

;
Home Documents Lisa FORMAT.Text
FORMAT.Text

FORMAT.Text

Lisa · TEXT
FilenameFORMAT.Text
Size0.01 MB
Subsection firmware / ROM88
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Contents
.Page
;++
;			Format
;
;--
; REGISTERS
;  IN
;	All =	Any value
;  OUT
;	All =	Destroyed
;
; CALLS
;	ClrBuf	Clears 524 byte buffer and other variables
;	SelSide	Selects side
;	Recall	Recalibrates disk to optical index sensor
;	WriTrk	Write no. of sectors in TempSec
;	VerTrk	Verifies no. of sectors in TempSec
;	SeekAlt	Seeks the teack in IIob+Track and sets speed
;	WrSynTrk	Writes bitslip FF's and A9's then sector 0
;	WArd16	Write sector x, both header and data fields
;	RdAdr	Reads sector header
;	Read16	Reads data fields
;	VfyCksum	Verifies checksum that was read
;	PreNib	Prenibblizes certain bytes for timing purposes
;
;++
.Page
Format	.Equ *				; Format entry point
FormTrk	.Equ *
	Jsr	ClrBuf			; Clear the buffer to be written
	Lda	#7
	Sta	FmtGap
	Jsr	RecalMtr			; Turn on motor & start from a known point (Track 0 )
	Bcs	FormRts			; Abort upon error from Recal

FormTop	Jsr	SeekAlt			; Go to othe track in IIob+Track & set speed
	Ldy	CurClass
	Lda	SecPrtTrk,y		; Fetch number of sectors in current track
	Sta	TempSec			; Save it for WriTrk

	Jsr	WriTrk			; Write a track full of sectors

	Lda	IIob+Command		; If a format track
	Cmp	#FrmTrk			; Then we're done-exit the routine
	Beq	VT00			; Command = FormatTrack (5)

	Lda	Iob+NoSides		; 1 = single side, 2 = double side
	Cmp	#2
	Bne	$39			; if <> 2 then go to incr to next track
	Lda	#20
	Sta	IIob+Side
	Jsr	WriTrk			; Now write second side
	Lda	#00
	Sta	IIob+Side			; Restore to side 0

$39	Inc	IIob+Track
	Lda	IIob+Track
	Cmp	#MaxTrack+1
	Bcc	FormTop			; Until we run out of tracks
	Dec	IIob+Track
	Bne	VT00			; Skip tunring the motor on

Verify	.Equ *				; Verify entry point
	Lda	#MaxTrack
	Sta	IIob+Track		; From inside of disk to outer edge
VerTrk	.Equ *
	Jsr	RecalMtr			; Turn on motor & start from a know point ( track 0 )
	Bcs	FormRts			; Abort upon error from Recal

VT00	.Equ *
	Jsr	SeekAlt			; Go to track in IIob+Track & set speed
	Ldy	CurClass
	Lda	SecPrTrk,y		; Fetch the number of sectors in current track
	Sta	TempSec			; Save it for WriTrk routine

	Jsr	VerTrk
	Bcs	FormErr			; Error, exit from routine

	Lda	IIob+Command		; If a verify track
	Cmp	#FrmtTrk			; Then we're done-exit the routine
	Bcs	$41			; Command = FormatTrack (5) or VerifyTrack (6)

	Lda	Iob+NoSides		; 1 = Single side, 2 = double side
	Cmp	#2
	Bne	$39
	Lda	#20
	Sta	IIob+Side
	Jsr	VerTrk			; Now verify side 1, track x
	Bcs	FormErr			; Error, exit from routine
	Lda	#00
	Sta	IIob+Side

$39	Dec	IIob+Track
	Bpl	VT00

$41	Clc
	Rts

FormErr	Lda	IIob+Track		; Current track number
	Sta	Trkjl0dNumb		; Save for host's usage
	Lda	IIob+Side			; Current side
	And	#20			; leave bit 5 -- side bit
	Beq	$17
	Lda	#1
$17	Sta	SideNumb			; Save for host's usage
	Lda	#SErrFrmt			; Format error code
FormRts	Rts

TooSml	.Equ *
	.Byte	0., 5., 10., 15.		; Not used
	.Byte	20., 25., 30., 35.		; 4:7
	.Byte	40., 45., 50., 55.		; 8:11
	.Byte	60., 65., 70., 75.		; 12:15

JustRit	.Equ *
	.Byte	108., 99., 90., 81., 72.	; Sectors in class * 9 bytes per sector

;++
;  WriTrk will physically format a disk in a 2:1 interleave.  It will
; write sector 0, sector x, sector 1, sector y, etc.
;--
WriTrk	.Equ				; Entry for writing a track of 524 byte sectors
	Jsr	SelSide			; Select proper side
	Lda	TempSec			; Total number of sectors on current track
	Sta	TotCnt			; Init total number of sectors on current track
	Lsr	A			; Divide by 2 and put remainder into carry
	Adc	#0			; Round up by adding carry
	Sta	HihCnt			; Init counter for high sector values
	Lda	#00
	Sta	CntPtr			; Init pointer for which count to use
	Sta	LowCnt			; For counting up from Sector 0
	Sta	IIob+Sector		; Start w/ sector 0

	Jsr	WrSynTrk			; Write 20 usec nibbles and A9's before sector 0
	Dec	TotCnt			; Subtract 1 from total sector count
	Inc	LowCnt			; Increment value to next low sector (1)
$23	Ldx	CntPtr			; Pointer to which cnt to use -- low or high
	Beq	$35			; If = 0 then increment to 1
	Ldx	#0FF			; If = 1 then decrement to 0
$35	Inx
	Stx	CntPtr
	Lda	LowCnt,x			; Fetch sector number
	Sta	IIob+Sector
	Inc	LowCnt,x			; Increment to next sector number
	Jsr	WAdr16			; Write address and data fields
	Dec	TotCnt			; Decrement total sector count
	Bne	$23			; When = 0 then all sectors are written

	Lda	#00
	Sta	IIob+Sector
	Jsr	RdAdrTmt			; If =  then less than 256 bytes were counted
	Bne	IncrG1			; >256 bytes so increase inter-sector gap

	Ldy	FmtGap
	Lda	TooSml,y
	Cmp	RangeL
	Bcs	DecrG1			; a > normal cnt with current Gap amount

	Ldy	CurClass
	Adc	JustRit,y
	Cmp	RangeL
	Bcs	WrTkDone			; A > range so all OK

IncrG1	Lda	#14.
	Cmp	FmtGap			; Limit to 14. self-sync groups of five
	Beq	WrTkDone
	Inc	FmtGap			; incr count for next track

WrTkDone	.Equ *
	Rts

DecrG1	.Equ	*
	Lda	#4.
	Cmp	FmtGap
	Beq	WrTkDone			; Minimum gap is 4 counts of 5 20 usec bytes

;++
;
;--
VerTrk	.Equ *
	Jsr	SelSide			; Select proper side
	Lda	#00
	Sta	IIob+Sector
	Sta	ScTrCnt
VfyTrk1	Lda	MaxRetry
	Sta	RetryCnt

VfyTrk2	Jsr	RdAdr			; Read sector address field
	Bcs	VfyErr
	Jsr	Read16			; Read sector data
	Bcs	VfyErr
	Jsr	VfyCksum			; Verify the checksum
	Bcs	VfyErr			; Must Be zero
VfRtry	Inc	IIob+Sector
	Lda	IIob+Sector
	Cmp	TempSec
	Bne	VfyTrk1			; If equal then carry will be set
	Lda	SctrCnt
	Bne	$74
	Clc
$74	Rts

VfyErr	Dec	RetryCnt
	Bne	VfyTrk2
	Ldy	SctrCnt
	Lda	IIob+Sector		; Current Sector Number
	Sta	SctrSav,y			; Save for host usage
	Inc	SctrCnt
	Bne	VfrTry			; Go to next sector and try again

ClrBuf	.Equ *
	Lda	#00			; Clear the total buffer area
	Tay
$05	Sta	Page02,y			; Zero part of the data buffer
	Sta	Page03,y			; Zero the rest of the data buffer
	Iny
	Bne	$05
	Ldy	#Bufr12SZ			; For 12 bytes header buffer
$10	Sta	Bufr12,y
	Dey
	Bpl	$10
	Sta	Cksum1			; Clear the three checksum butes
	Sta	Cksum2
	Sta	Cksum3
	Jmp	PreNib			; Create 5 composite bytes & return to caller
Home Documents Macintosh M0110a 341 0322a.Txt
M0110a 341 0322a.Txt

M0110a 341 0322a.Txt

Macintosh · TXT
Filenamem0110a_341-0322a.txt
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Contents
;       Date:           Tue May 05 18:01:12 2020
                                ;
                                ;       CPU:            Intel 8048 (MCS-48 family)
                                ;
                                ;
                                ;
                                        org     00000H
                                ;
0000                            L0000:
0000 : E5               " "             sel     mb0
0001 : 04 1A            "  "            jmp     L001A
                                ;
0003 : E5               " "             sel     mb0
0004 : 04 1A            "  "            jmp     L001A
                                ;
0006 : 00               " "             nop
0007 : E5               " "             sel     mb0
0008 : 14 32            " 2"            call    L0032
000A : 76 00            "v "            jf1     L0000
000C : B5               " "             cpl     f1
000D : D5               " "             sel     rb1
000E : B8 29            " )"            mov     r0,#029H
0010 : A0               " "             mov     @r0,a
0011 : 23 5D            "#]"            mov     a,#05DH
0013 : 62               "b"             mov     t,a
0014 : FC               " "             mov     a,r4
0015 : C6 18            "  "            jz      L0018
0017 : CC               " "             dec     r4
0018                            L0018:
0018 : 04 34            " 4"            jmp     L0034
                                ;
001A                            L001A:
001A : 15               " "             dis     i
001B : 85               " "             clr     f0
001C : A5               " "             clr     f1
001D : C5               " "             sel     rb0
001E : 23 FF            "# "            mov     a,#0FFH
0020 : 39               "9"             outl    p1,a
0021 : 3A               ":"             outl    p2,a
0022 : 27               "'"             clr     a
0023 : D7               " "             mov     psw,a
0024 : B8 3F            " ?"            mov     r0,#03FH
0026                            L0026:
0026 : A0               " "             mov     @r0,a
0027 : E8 26            " &"            djnz    r0,L0026
0029 : 14 32            " 2"            call    L0032
002B : 23 5D            "#]"            mov     a,#05DH
002D : 62               "b"             mov     t,a
002E : 25               "%"             en      tcnti
002F : 55               "U"             strt    t
0030 : 24 02            "$ "            jmp     L0102
0032                            L0032:
0032 : 93               " "             retr
                                ;
0033 : 00               " "             nop
0034                            L0034:
0034 : B8 28            " ("            mov     r0,#028H
0036 : F0               " "             mov     a,@r0
0037 : 96 5F            " _"            jnz     L005F
0039 : 8A 80            "  "            orl     p2,#080H
003B : 0A               " "             in      a,p2
003C : 53 80            "S "            anl     a,#080H
003E : 96 DE            "  "            jnz     L00DE
0040 : BE 08            "  "            mov     r6,#008H
0042                            L0042:
0042 : 9A BF            "  "            anl     p2,#0BFH
0044 : BF 23            " #"            mov     r7,#023H
0046                            L0046:
0046 : EF 46            " F"            djnz    r7,L0046
0048 : 8A 40            " @"            orl     p2,#040H
004A : BF 0D            "  "            mov     r7,#00DH
004C                            L004C:
004C : EF 4C            " L"            djnz    r7,L004C
004E : 0A               " "             in      a,p2
004F : 53 80            "S "            anl     a,#080H
0051 : 40               "@"             orl     a,@r0
0052 : E7               " "             rl      a
0053 : A0               " "             mov     @r0,a
0054 : BF 17            "  "            mov     r7,#017H
0056                            L0056:
0056 : EF 56            " V"            djnz    r7,L0056
0058 : EE 42            " B"            djnz    r6,L0042
005A : B8 28            " ("            mov     r0,#028H
005C : A0               " "             mov     @r0,a
005D : BC 0C            "  "            mov     r4,#00CH
005F                            L005F:
005F : B8 28            " ("            mov     r0,#028H
0061 : F0               " "             mov     a,@r0
0062 : D3 14            "  "            xrl     a,#014H
0064 : C6 79            " y"            jz      L0079
0066 : F0               " "             mov     a,@r0
0067 : D3 10            "  "            xrl     a,#010H
0069 : C6 7F            "  "            jz      L007F
006B : F0               " "             mov     a,@r0
006C : D3 16            "  "            xrl     a,#016H
006E : C6 8F            "  "            jz      L008F
0070 : F0               " "             mov     a,@r0
0071 : D3 36            " 6"            xrl     a,#036H
0073 : C6 95            "  "            jz      L0095
0075 : B0 00            "  "            mov     @r0,#000H
0077 : 04 DE            "  "            jmp     L00DE
                                ;
0079                            L0079:
0079 : 54 9B            "T "            call    L029B
007B : C6 8B            "  "            jz      L008B
007D : 04 9B            "  "            jmp     L009B
                                ;
007F                            L007F:
007F : FC               " "             mov     a,r4
0080 : C6 8B            "  "            jz      L008B
0082 : 54 9B            "T "            call    L029B
0084 : 96 9B            "  "            jnz     L009B
0086 : FB               " "             mov     a,r3
0087 : C6 DE            "  "            jz      L00DE
0089 : 04 9B            "  "            jmp     L009B
                                ;
008B                            L008B:
008B : BB 7B            " {"            mov     r3,#07BH
008D : 04 9B            "  "            jmp     L009B
                                ;
008F                            L008F:
008F : 85               " "             clr     f0
0090 : 95               " "             cpl     f0
0091 : BB 0B            "  "            mov     r3,#00BH
0093 : 04 9B            "  "            jmp     L009B
                                ;
0095                            L0095:
0095 : 85               " "             clr     f0
0096 : 95               " "             cpl     f0
0097 : BB 7D            " }"            mov     r3,#07DH
0099 : 04 9B            "  "            jmp     L009B
                                ;
009B                            L009B:
009B : 8A 80            "  "            orl     p2,#080H
009D : 0A               " "             in      a,p2
009E : 53 80            "S "            anl     a,#080H
00A0 : 96 A7            "  "            jnz     L00A7
00A2 : FC               " "             mov     a,r4
00A3 : 96 DE            "  "            jnz     L00DE
00A5 : 04 D8            "  "            jmp     L00D8
                                ;
00A7                            L00A7:
00A7 : FB               " "             mov     a,r3
00A8 : 96 AC            "  "            jnz     L00AC
00AA : 54 A0            "T "            call    L02A0
00AC                            L00AC:
00AC : BE 08            "  "            mov     r6,#008H
00AE                            L00AE:
00AE : F7               " "             rlc     a
00AF : F6 C6            "  "            jc      L00C6
00B1 : 9A 3F            " ?"            anl     p2,#03FH
00B3 : BF 19            "  "            mov     r7,#019H
00B5                            L00B5:
00B5 : EF B5            "  "            djnz    r7,L00B5
00B7 : 8A 40            " @"            orl     p2,#040H
00B9 : BF 1B            "  "            mov     r7,#01BH
00BB                            L00BB:
00BB : EF BB            "  "            djnz    r7,L00BB
00BD : EE AE            "  "            djnz    r6,L00AE
00BF : B6 00            "  "            jf0     L0000
00C1 : 04 D8            "  "            jmp     L00D8
                                ;
00C3 : 00               " "             nop
00C4 : 04 00            "  "            jmp     L0000
                                ;
00C6                            L00C6:
00C6 : 8A 80            "  "            orl     p2,#080H
00C8 : 9A BF            "  "            anl     p2,#0BFH
00CA : BF 19            "  "            mov     r7,#019H
00CC                            L00CC:
00CC : EF CC            "  "            djnz    r7,L00CC
00CE : 8A 40            " @"            orl     p2,#040H
00D0 : BF 19            "  "            mov     r7,#019H
00D2                            L00D2:
00D2 : EF D2            "  "            djnz    r7,L00D2
00D4 : EE AE            "  "            djnz    r6,L00AE
00D6 : B6 00            "  "            jf0     L0000
00D8                            L00D8:
00D8 : 27               "'"             clr     a
00D9 : AB               " "             mov     r3,a
00DA : B8 28            " ("            mov     r0,#028H
00DC : A0               " "             mov     @r0,a
00DD : AC               " "             mov     r4,a
00DE                            L00DE:
00DE : C7               " "             mov     a,psw
00DF : 07               " "             dec     a
00E0 : 53 07            "S "            anl     a,#007H
00E2 : 03 FD            "  "            add     a,#0FDH
00E4 : F6 00            "  "            jc      L0000
00E6 : 03 03            "  "            add     a,#003H
00E8 : E7               " "             rl      a
00E9 : 03 09            "  "            add     a,#009H
00EB : A8               " "             mov     r0,a
00EC : F0               " "             mov     a,@r0
00ED : 53 0F            "S "            anl     a,#00FH
00EF : 03 FD            "  "            add     a,#0FDH
00F1 : F6 00            "  "            jc      L0000
00F3 : 25               "%"             en      tcnti
00F4 : B8 29            " )"            mov     r0,#029H
00F6 : F0               " "             mov     a,@r0
00F7 : C5               " "             sel     rb0
00F8 : 93               " "             retr
                                ;
00F9 : 00               " "             nop
00FA : 00               " "             nop
00FB : 00               " "             nop
00FC : 00               " "             nop
00FD : 00               " "             nop
00FE : 04 00            "  "            jmp     L0000
0100 : 04 00            "  "            jmp     L0000
                                ;
0102                            L0102:
0102 : A5               " "             clr     f1
0103 : C5               " "             sel     rb0
0104 : B9 35            " 5"            mov     r1,#035H
0106 : 25               "%"             en      tcnti
0107 : B8 2A            " *"            mov     r0,#02AH
0109 : BF FF            "  "            mov     r7,#0FFH
010B : BA 01            "  "            mov     r2,#001H
010D : BB 01            "  "            mov     r3,#001H
010F : D5               " "             sel     rb1
0110 : BD 01            "  "            mov     r5,#001H
0112 : C5               " "             sel     rb0
0113 : 24 1C            "$ "            jmp     L011C
                                ;
0115 : 00               " "             nop
0116 : 04 00            "  "            jmp     L0000
                                ;
0118                            L0118:
0118 : C5               " "             sel     rb0
0119 : FA               " "             mov     a,r2
011A : 12 8D            "  "            jb0     L018D
011C                            L011C:
011C : 00               " "             nop
011D : A5               " "             clr     f1
011E : 14 32            " 2"            call    L0032
0120 : 25               "%"             en      tcnti
0121 : 55               "U"             strt    t
0122 : 1F               " "             inc     r7
0123 : D5               " "             sel     rb1
0124 : FD               " "             mov     a,r5
0125 : 52 2E            "R."            jb2     L012E
0127 : 12 3A            " :"            jb0     L013A
0129 : 32 4D            "2M"            jb1     L014D
012B : 00               " "             nop
012C : 04 00            "  "            jmp     L0000
                                ;
012E                            L012E:
012E : C5               " "             sel     rb0
012F : FB               " "             mov     a,r3
0130 : E7               " "             rl      a
0131 : AB               " "             mov     r3,a
0132 : D2 02            "  "            jb6     L0102
0134 : 0A               " "             in      a,p2
0135 : 5B               "["             anl     a,r3
0136 : C6 6E            " n"            jz      L016E
0138 : 24 5B            "$["            jmp     L015B
                                ;
013A                            L013A:
013A : C5               " "             sel     rb0
013B : 23 FF            "# "            mov     a,#0FFH
013D : 90               " "             movx    @r0,a
013E : FB               " "             mov     a,r3
013F : 37               "7"             cpl     a
0140 : 39               "9"             outl    p1,a
0141 : 08               " "             ins     a,bus
0142 : 37               "7"             cpl     a
0143 : 5A               "Z"             anl     a,r2
0144 : 89 FF            "  "            orl     p1,#0FFH
0146 : 96 6E            " n"            jnz     L016E
0148 : 24 5B            "$["            jmp     L015B
                                ;
014A : 00               " "             nop
014B : 04 00            "  "            jmp     L0000
                                ;
014D                            L014D:
014D : C5               " "             sel     rb0
014E : 23 FF            "# "            mov     a,#0FFH
0150 : 90               " "             movx    @r0,a
0151 : FB               " "             mov     a,r3
0152 : 37               "7"             cpl     a
0153 : 3A               ":"             outl    p2,a
0154 : 08               " "             ins     a,bus
0155 : 37               "7"             cpl     a
0156 : 5A               "Z"             anl     a,r2
0157 : 8A FF            "  "            orl     p2,#0FFH
0159 : 96 6E            " n"            jnz     L016E
015B                            L015B:
015B : FA               " "             mov     a,r2
015C : 50               "P"             anl     a,@r0
015D : C6 65            " e"            jz      L0165
015F : FA               " "             mov     a,r2
0160 : 37               "7"             cpl     a
0161 : 50               "P"             anl     a,@r0
0162 : A0               " "             mov     @r0,a
0163 : 24 88            "$ "            jmp     L0188
                                ;
0165                            L0165:
0165 : FA               " "             mov     a,r2
0166 : 51               "Q"             anl     a,@r1
0167 : 96 DF            "  "            jnz     L01DF
0169 : 24 88            "$ "            jmp     L0188
                                ;
016B : 00               " "             nop
016C                            L016C:
016C : 04 00            "  "            jmp     L0000
                                ;
016E                            L016E:
016E : FF               " "             mov     a,r7
016F : E3               " "             movp3   a,@a
0170 : 92 79            " y"            jb4     L0179
0172 : FE               " "             mov     a,r6
0173 : 32 88            "2 "            jb1     L0188
0175 : 03 FD            "  "            add     a,#0FDH
0177 : F6 6C            " l"            jc      L016C
0179                            L0179:
0179 : FA               " "             mov     a,r2
017A : 50               "P"             anl     a,@r0
017B : 96 82            "  "            jnz     L0182
017D : FA               " "             mov     a,r2
017E : 40               "@"             orl     a,@r0
017F : A0               " "             mov     @r0,a
0180 : 24 88            "$ "            jmp     L0188
                                ;
0182                            L0182:
0182 : FA               " "             mov     a,r2
0183 : 51               "Q"             anl     a,@r1
0184 : C6 BB            "  "            jz      L01BB
0186 : 24 88            "$ "            jmp     L0188
                                ;
0188                            L0188:
0188 : FA               " "             mov     a,r2
0189 : E7               " "             rl      a
018A : AA               " "             mov     r2,a
018B : 24 18            "$ "            jmp     L0118
                                ;
018D                            L018D:
018D : 14 32            " 2"            call    L0032
018F : C5               " "             sel     rb0
0190 : 18               " "             inc     r0
0191 : 19               " "             inc     r1
0192 : D5               " "             sel     rb1
0193 : FD               " "             mov     a,r5
0194 : C5               " "             sel     rb0
0195 : 32 A1            "2 "            jb1     L01A1
0197 : FB               " "             mov     a,r3
0198 : E7               " "             rl      a
0199 : AB               " "             mov     r3,a
019A : 12 B2            "  "            jb0     L01B2
019C : 24 1C            "$ "            jmp     L011C
                                ;
019E : 00               " "             nop
019F : 04 00            "  "            jmp     L0000
                                ;
01A1                            L01A1:
01A1 : FB               " "             mov     a,r3
01A2 : E7               " "             rl      a
01A3 : AB               " "             mov     r3,a
01A4 : 52 A8            "R "            jb2     L01A8
01A6 : 24 1C            "$ "            jmp     L011C
                                ;
01A8                            L01A8:
01A8 : D5               " "             sel     rb1
01A9 : BD 04            "  "            mov     r5,#004H
01AB : 00               " "             nop
01AC : C5               " "             sel     rb0
01AD : FB               " "             mov     a,r3
01AE : 77               "w"             rr      a
01AF : AB               " "             mov     r3,a
01B0 : 24 1C            "$ "            jmp     L011C
                                ;
01B2                            L01B2:
01B2 : D5               " "             sel     rb1
01B3 : BD 02            "  "            mov     r5,#002H
01B5 : C5               " "             sel     rb0
01B6 : 24 1C            "$ "            jmp     L011C
                                ;
01B8 : 00               " "             nop
01B9 : 04 00            "  "            jmp     L0000
                                ;
01BB                            L01BB:
01BB : FF               " "             mov     a,r7
01BC : E3               " "             movp3   a,@a
01BD : C6 88            "  "            jz      L0188
01BF : 53 0A            "S "            anl     a,#00AH
01C1 : C6 E1            "  "            jz      L01E1
01C3 : 37               "7"             cpl     a
01C4 : 72 E1            "r "            jb3     L01E1
01C6 : 54 7E            "T~"            call    L027E
01C8 : 03 FD            "  "            add     a,#0FDH
01CA : E6 88            "  "            jnc     L0188
01CC : BC 71            " q"            mov     r4,#071H
01CE : 54 87            "T "            call    L0287
01D0                            L01D0:
01D0 : 54 7E            "T~"            call    L027E
01D2 : 03 FE            "  "            add     a,#0FEH
01D4 : E6 88            "  "            jnc     L0188
01D6 : BC 79            " y"            mov     r4,#079H
01D8 : 54 87            "T "            call    L0287
01DA : 44 1D            "D "            jmp     L021D
         …

Showing first 20,000 characters of 47,641 total. Open the full document →

Home Documents Lisa HIMEM.Text
HIMEM.Text

HIMEM.Text

Lisa · TEXT
FilenameHIMEM.Text
Size0.00 MB
Subsection firmware / ROM88
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Contents
.Page
;+
;
;			Himem
;		Welcome to Vector City!
; Himem Constants
;
;--

	.Org	02000-00D			; Length of high memory constants
Cpyrt	.Ascii	"C83APPLE"		; This'l show em, we mean business!
RstJmp	.Byte	04C			; A jump vector to the Restart code
	.Word	Restart			; Restart 6504 reset vector
	.Byte	0, 0			; Used to hold checksum for ROM verification
Home Documents Lisa TRKCLASS.Text
TRKCLASS.Text

TRKCLASS.Text

Lisa · TEXT
FilenameTRKCLASS.Text
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.Page
;++
;			TrackClass will return the class (from 0 to 8) of
;		the track in IIOB+Track in the "Y" register
;
;		returns:		"Y" reg = class of track
;					"A" reg = IIOB+Track
;					"X" reg = unchanged
;--

TrkClss	.Equ *				; Entry point
	Lda	IIOB+Track		; Fetch current track value
	Ldy	#MaxClass		; Maximum class value
$21	Cmp	ClssTbl,Y		; Track >= Table entry?
	Bcs	$42			; Yep
	Dey
	Bne	$21			; Try the next track class
$42	Rts				; "Y" reg = track class value


ClssTbl	.Equ *				; Start of track class table
	.Byte 00			; Track  0:15
	.Byte 10			; Track 16:31
	.Byte 20			; Track 32:47
	.Byte 30			; Track 48:63
	.Byte 40			; Track 64:79
Home Documents Lisa SY.Text
SY.Text

SY.Text

Lisa · TEXT
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Contents
.ABSOLUTE
.PROC LISA
.LIST
.TITLE "Sony DRIVER FOR LISA"
.INCLUDE VAR
.ORG	1000
.INCLUDE TABLES
.INCLUDE TRKCLASS
.INCLUDE FR3TO1
.INCLUDE DENIBBLE
.INCLUDE NEWRWADDR
.INCLUDE Interface
.INCLUDE LOOP
.INCLUDE CLRTRK
.INCLUDE PRENIB
.INCLUDE CMD
.INCLUDE SEEK
.INCLUDE WAITROM
.INCLUDE NMREAD16
.INCLUDE READ
.INCLUDE CRECKSUM
.INCLUDE VFYCKSUM
.INCLUDE WRITE
.INCLUDE WRITE16
.INCLUDE FORMAT
.INCLUDE RECAL
.INCLUDE Npwm
.INCLUDE HIMEM
.End
Home Documents Macintosh TSM RE.Txt
TSM RE.Txt

TSM RE.Txt

Macintosh · TXT
FilenameTSM_RE.txt
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Subsection mac_plus / hals / 341-0522-a
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TSM : 16R4

TSM is a 16R4 device whose major function is control of the dynamic RAM. For
inputs, it has the decoded RAM enable signal, along with the address and data
strobes from the processor which signify whether the data transfer will be low
byte, hi byte, or word. From these the RAS and CAS strobes are generated, and
the row/column address multiplexer is controlled. Until there were PALs, this
type of dynamic RAM control function required either about 10-20 discrete TTL
packages, or a 40 pin LSI dynamic RAM controller which usually didn't do what
you wanted anyway.

/TSEN0  /CS     11              10              GND
/CASL    O      12              9        I      /LDS
/CASR    O      13              8        I      /UDS
/RAS     R      14              7        I      /AS
TC       R      15              6        I      /ROM
C1M      R      16              5        I      /RAM
C4M      R      17              4        I      VID/u*
C2M      O      18              3        I      C8M
/DTACK   O      19              2        I      C16M
Vcc             20              1       CLK     C16M

From Kryten's (now gone) page:

Apple Mac Timing State Machine, PAL16R8

NB: Not verified yet!

PAL16R8  PAL DESIGN SPECIFICATIONS

16MBUF C16M 8M MU RAMEN ROMEN AS UDS LDS GND 
TSEN CAS0 CAS1 RAS TC 1M 4M 2M DTACK VCC

RAS is the DRAM Row Address Strobe.

RAS: =       /4M *             /RAS
     +  8M *  4M *             /RAS + 
     + /8M *  4M *       /2M * /RAS
     +  8M * /4M *  1M *        RAS
     +  8M * /4M * /1M *  2M *  RAS
     + /8M *  4M * /1M *        RAS *  LDS
     + /8M *  4M * /1M *        RAS *  UDS
     + /8M *  4M * /1M *        RAS * /LDS * /UDS * /CAS0
     + 

TC goes to the LAG and to the video counter (U1F)

TC:= 8M + /4M + 2M +  /1M + RAS

1M: =      /8M *  4M * /2M * 1M * /RAS + 
     /1M *  8M * /4M * /RAS + 
     /1M * /8M *  4M * 2M * /RAS + 
     /1M *              RAS + 
     /1M * /8M * /4M * /RAS + 
     /1M * 8M *   4M * /RAS

4M: =                    1M *  RAS + 
       8M *  4M *  2M * /1M *  RAS + 
      /8M * /4M *       /1M *  RAS + 
       8M * /4M *  2M * /1M *  RAS + 
      /8M *  4M * /2M *       /RAS + 
there may be a line missing here..... 

2M: = /C16M *       /8M * /4M * /RAS
    +         /2M + /8M + /4M 
    +         /2M + /1M + * /TC
    +  C16M * /2M
    + /C16M * /8M * /4M * /1M * RAS * /ROMEN * /RAMEN * /AS
    + /2M * 4M
    + /2M * 8M * /4M *1M * MU

DTACK := /C16M * /8M * /4M *        /RAS * /AS * /ROMEN *  RAMEN
      +  /C16M * /8M * /4M * /1M  * /RAS * /AS * /RAMEN *  ROMEN
      +  /C16M * /8M * /4M *  1M  * /RAS * /AS * /RAMEN *  ROMEN * /MU
      +  /C16M * /8M *  4M * /1M  *  RAS * /AS * /RAMEN * /ROMEN
      +  /DTACK * /UDS
      +  /DATACK * /LDS
      +  /DATACK * /RAS

This is probably not right for the Mac Plus...

CAS0: =  4M * /2M *       /RAS * /DTACK * /RAMEN * ROMEN * /LDS * MU
      +  4M * /2M * 1M * /RAS * MU
      + /CAS0 
      + /RAS
      +  8M + 4M + /2M * /1M * RAS * /DTACK
      + /CAS0 * /2M + /1M

CAS1: = 4M * /2M *              /RAS * /DTACK * /RAMEN * ROMEN * /UDS * MU
      + 4M * /2M * 1M *         /RAS *                                  MU
      +                 /CAS1 + /RAS
Home Documents Lisa VAR.Text
VAR.Text

VAR.Text

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Subsection firmware / ROM88
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.PAGE

;---
;				ZERO PAGE MAPPING
;
;	The following equates are for dividing RAM into logical areas;
;	however, as the code grew, this convention was not strictly adhered
;	to and therefore one will find both "LOCAL" and "GLOBAL" variables
;	scattered throughout the RAM area
;+++

IOB	.Equ 00	;  INPUT OUTPUT BLOCK
SHARERAM	.Equ 10	;  READ/WRITE SHARED RAM, INITIALIZED BY 6504 ON BOOT
STATUS	.Equ 20	;  READ ONLY STATUS FROM THE 6504
IIOB	.Equ 30	;  INTERNAL IOB
GLOBALS	.Equ 40	;  6504 INTERNAL GLOBALS
LOCALS	.Equ 68	;  LOCAL VARIABLES

;;	THESE APPEAR, FROM THE LISTING PROVIDED, TO BE HEX NUMBERS UNLESS FOLLOWED BY A DECIMAL
;;	1/6/89 ARS

.PAGE

;---
;
;				IOB
;
;  THE IOB IS ALWAYS COPIED INTO THE INTERNAL IOB (IIOB) AREA BEFORE USAGE
;  SO THAT THE 68K CAN START TO BUILD A NEW COMMAND INTO THE IOB AS SOON AS
;  POSSIBLE.  ALL REFERENMCES TO THE IOB OF IIOB ARE DONE IN THE FOLLOWING
;  FORMAT:
;	IOB	IIOB
;	--------	--------
;  GOBYTE	IOB+GOBYTE	IIOB+GOBYTE
;  DRIVE	IOB+DRIVE	IIOB+DRIVE
;
;+++
IOBSIZE	.Equ 07	;  SIZE OF IOB BLOCK USED FOR PARAMETER PASSING
GOBYTE	.Equ 00	;  COMMAND BYTER FROM 68K

;	00	COMMAND ACCEPTED BY THE 6504, 68K MAY ISSUE A NEW COMMAND
;	80-89	COMMAND FROM 68K TO 6504
;	80	NULL, TESTS HANDSHAKE
;	81	RWTS COMMAND, COMMAND CODE IN 'COMMAND'
;	83	SEEK
;	84	CALL ADDRESS IN 6504
;	85	CLEAR STATUS
;	86	SET MASK
;	87	CLEAR MASK
;	88	WAIT IN ROM
;	89	Go jump to self forever (Their case change ARS)
;
;	01-7f,82,90-ff		*** RESERVED ***

COMMAND	.Equ 01	;  RWTS COMMAND CODE

;	00	READ	Read Read the Data @ Drive/Side/Track/Sector
;	01	WRITE	Write Read the Data @ Drive/Side/Track/Sector
;	02	UNCLAMP	Unclamp the disk in Drive
;	03	FORMAT	Format the disk in Drive
;	04	VERIFY	Verify the disk in Drive
;	05	FORMAT TRACK	Format single Track on the disk in Drive
;	06	VERIFY TRACK	Verify single Track on the disk in Drive
;	07	READBF	Read w/o checksum verification
;	08	WRITEBF	Write w/o checksum creation
;	09	CLAMP	Clamp the disk in Drive
;	0A-FF		*** RESERVED ***

MASK	.Equ COMMAND	;  MASK FOR SETTING AND RESETTING IMSK & IST

;	08	SET OR CLEAR INTERRUPT MASK FOR UPPER DRIVE
;	80	SET OR CLEAR INTERRUPT MASK FOR LOWER DRIVE
;	01	CLEAR DISK INSERTED INTERRUPT FOR UPPER DRIVE
;	10	CLEAR DISK INSERTED INTERRUPT FOR LOWER DRIVE
;	02	CLEAR BUTTOM PRESSED INTERRUPT FOR UPPER DRIVE
;	20	CLEAR BUTTOM PRESSED INTERRUPT FOR LOWER DRIVE
;	04	CLEAR R/W COMMAND COMPLETED INTERRUPT FOR UPPER DRIVE
;	40	CLEAR R/W COMMAND COMPLETED INTERRUPT FOR LOWER DRIVE

ADRL	.Equ COMMAND	;  LOW BYTE OF ADDRESS FOR 6504 CALL
ADRH	.Equ ADRL+1	;  HIGH BYTE OF ADDRESS FOR 6504 CALL
		;  A call to "1FFB" will reset the 65404

DRIVE	.Equ 02	;  DRIVE NUMBER

;	00	DRIVE 0 UPPER DRIVE
;	80	DRIVE 80	LOWER DRIVE

SIDE	.Equ 03	;  SIDE NUMBER

;	00	SIDE 0 UPPER SIDE OF MEDIA
;	01	SIDE 1 LOWER SIDE OF MEDIA

SECTOR	.Equ 04	; SECTOR NUMBER

;	00-15	MAXIMUM DEPENDES ON TRACK NUMBER

TRACK	.Equ 05	;  TRACK NUMBER

;	00-2D	46 TRACKS TOTAL

SPEED	.Equ 06	;  SPEED OVERRIDE

;	00	NOOVERRIDE, SPEED IN DEPENDING ON TRACK NUMBER
;	01-FF	Modifier value added to nominal speed

FMTCNFN	.Equ 07	;  Format configuration byte
		;  Used to ensure format is not executed by mistake
;	FF	FMTCNFM must be = FF for foramt/format track to work

ERRSTAT	.Equ 08	;  ERROR STATUS, RETURNED AFTER R/W COMMANDS
		;  See constants for current error code values

DISKID	.Equ 09	; Current id of the disk last accessed

;	00	UIniFile/DuoFile disk
;	01	Lisa disk
;	02	Macintosh disk

NoSides	.Equ 0A	;  Number of sides of disk drive

DrvError	.Equ 0B	;  Hard errors get returned throught his byte

HostSeek	.Equ 0C	;  When moving the head this location = 'FF'

SekErr	.Equ 0D	;  When seek does not handshake then = '0F'

.Page

;--
;			Shared RAM
;
;  SHARED RAM COMES IN TWO FLAVOERS:  'READ/WRITE' AND 'READ ONLY'.  THE 68K CAN,
;  OF COURSE, READ AND WRITE TO ANY BYTE IN THE RAM AT ANY TIME BUT THIS IS NOT
;  VERY WISE, (ONE MIGHT SAY VERY FOOLISH...), SO THE BY 'READ ONLY' WE MEAN
;  MEMORY THAT NEVER SHOULD BE WRITTEN TO BY THE 68K BUT IS VALID TO READ AT
;  ANY TIME.  TYPICAL 'READ ONY' VARIABLES ARE THE STATUS FLAGS CLMED0 AND
;  CLMPED80 THAT TELLS THE 68K THAT A DISK IS CLAMPED IN DRIVE 0 OR 80
;
;  'READ/WRITE' SHARED MEMORY IS, FOR EXAMPLE, THE IOB BUT IN THIS CASE IT IS
;  A FAMILY OF 'CONSTANTS' SET UP ON COLD START BY THE 6504 TO THEIR DEFAULT
;  VALUES, BUT THEY CAN BE CHANGED AT ANY TIME BY THE 68K TO ANY VALUE.  THERE
;  IS NO CHECKING OF THE RANGE OF THESE VALUES O THE NEW ONE BETTER MAKE SENSE
;  OR THE 6504 MIGHT GO OF TO NEVER, NEVER LAND...
;
;		SHARED:  READ/RWITE
;++

MSpdTbl	.Equ ShareRam
SCDLY	.Equ SHARERAM+5.	;  Speed change delay in 5 ms intervals
HEADELAY	.Equ SHARERAM+6.	;  Head settling time in 5 ms intervals
MAXDDLY	.Equ SHARERAM+7.	;  Timer value in 2/3 second before motor off
ROMIDNUM	.Equ SHARERAM+8.	;  ROM identification number ( 0018/FCC031 )
MAXRETRY	.Equ SHARERAM+9.	;  Maximum number of retries during a read/rwite
MAXRECAL	.Equ SHARERAM+10.	;  Maximum number of recalibrations during a r/w
StpDly	.Equ SHARERAM+11.	;  Step dely time in 100 usec intervals
MONDLY	.Equ SHARERAM+12.	;  Motor on delay time in 5 ms intervals

.Page

;++
;		SHARED:  READ ONLY
;--

Clamped	.Equ Status	;  Disk in Place (=0 EMPYT, =FF CLAMPED)
MtrOn	.Equ Clamped+1	;  DRIVE MOTOR SELECT (0=OFF, FF=ON)

CurTrack	.Equ Status+2	;  value of current track
CurClass	.Equ CurTrack+1	;  Current track class (0:  4)

DrvConn	.Equ Status+4	;  Will be 'FF' if a drive is physically there
FmtType	.Equ DrvConn+1	;  '2' for single, '22' for double sideed

RetryCnt	.Equ Status+6	;  RETRY COUNT
RecalCnt	.Equ RetryCnt+1	;  RECALIBRATION COUNT

ImAlive	.Equ Status+8	; THIS VARIABLE SPINNS AS LONG AS THE MAIN LOOP IS EXECUTING

Counter	.Equ Status+9.	;  GENERAL COUNTER
HoldInx	.Equ Counter+1	;  Holds command index temporarily
FmtGap	.Equ Counter+2	;  Amt * 5 of 20 usec 'FF's to write as selfsync

Imsk	.Equ Status+12.	;  Bits 7 & 3 are mask; if set the drive enabled
DipIntr	.Equ Imsk+1	;  Flag reflects DIP interrupt
OkToGo	.Equ Imsk+2	;  REFLECTS FDIR (=0, FDIRL; <>0, FDIRH)
IST	.Equ Imsk+3	;  INTERRUPT STATUS

;	Bits of IST are numbered for LSb (0) to MSb (7)
;
;	Bit	Meaning
;	---	-------
;	0	Drive 0 disk inserted
;	1	Drive 0 button pressed
;	2	Drive 0 R/W completed
;	3	Logical OR of bit 0,1 & 2
;	4	Drive 80 disk inserted
;	5	Drive 80 button pressed
;	6	Drive 80 R/W completed
;	7	Logical OR of bit 4,5 & 6

AdrMk1	.Equ	IIob+8	;  5 values that indicate start and end of address field
AdrMk2	.Equ	AdrMk1+1
AdrMk3	.Equ	AdrMk1+2
AdrMk4	.Equ	AdrMk1+3
AdrMk5	.Equ	AdrMk1+4

.Page
		; Following 3 byte counter controls both testing
		; for DIP and shutting off teh motors.  When
WtLow	.Equ Globals	; the low 2 bytes = 0 then test for DIP. When
WtMid	.Equ WtLow+1	; the third byte becomes 0 the heads are parked
WtHih	.Equ WTLow+2	; and the motors are turned off
		; For timing and space purposes during writeg
		; of data, an indexed by "y" through zero
INXPTRL	.Equ Globals+3	; pge instruction is used.  The two bytes
INXPTRH	.Equ INXPTRL+1	; hold the base address for the index\.

		; Some constants for timing purposes
K000	.Equ Globals+5	; A constant '00'
K0FF	.Equ K000+1	; A constant 'FF'

		; Following 8 locations hold error counters for
		; various read errors.  The first three are for
		; error w/ reading data and the last five are
		; for errors associated w/ the header.
STSLP	.Equ GLOBALS+8.	; Read Data Starting Bitslip
BSCNT	.Equ StSlp+1	; Read Data ending Bitslip
CSERROR	.Equ StSlp+2	; Read data Checksum error
RASTRT	.Equ StSlp+3	; Read Address Starting Bitslip
RAEND	.Equ StSlp+4	; Read Address Ending Bitslip
RASCTR	.Equ StSlp+5	; Read Address wrong sector
RATRK	.Equ StSlp+6	; Read Address wrong track
RACSUM	.Equ StSlp+7	; Read Address Checksum error
ERRLEN	.Equ 7	; 8 bytes, zero based

CSMFND	.Equ Globals+16.	; CHECKSUM read from disk
VOLFND	.Equ CsmFnd+1		; 0 = UniFile/DuoFile, 1 = Lisa, 2 = Mac
SDFND	.Equ CsmFnd+2		; SIDE FOUND
SECFND	.Equ CsmFnd+3		; SECTOR FOUND
TRKFND	.Equ CsmFnd+4		; TRACK FOUND
CSUM	.Equ CsmFnd+5		; Checksum calculated from ADDRESS data
ADRSLEN	.Equ 4		; LENGTH OF ADDRESS HEADER - 1

TrkFlg	.Equ Globals+22.
MtrFlg	.Equ TrkFlg+1
StpAmt	.Equ TrkFlg+2
Direct	.Equ TrkFlg+3

IndexL	.Equ Globals+26.
IndexH	.Equ IndexL+1
RangeL	.Equ IndexL+2
RangeH	.Equ IndexL+3

CPBY01	.Equ Globals+30.	; Composite byte formed from BUFFER[ 2FF:301 ]
CPBY02	.EQY CPBY01+1		; [ 3FE:3FF ]

CPCKSUM	.Equ Globals+32.	; Composite byte formed from 3 checksum bytes
CKSUM1	.Equ CPCKSUM+1		; First checksum byte
CKSUM2	.Equ CPCKSUM+2		; Second shecksum byte
CKSUM3	.Equ CPCKSUM+3		; Third checksum byte

TCKSM1	.Equ Globals+36.	; During a read of data, the checksum is read
TCKSM2	.Equ TCKSM1+1		; into "CKSM1..3".  A new checksum is created
TCKSM3	.Equ TCKSM1+2		; and stored in these 3 bytes to verify matters

TEMPSEC	.Equ Globals+39.	; TEMPRARY SECTOR COUNTER USED BY FORMAT

.Page

;--
;			LOCAL VARIABLES USED IN ONE OR SEVERAL ROUTINES
;++

RWCSMFLG	.Equ LOCALS		; Flag fro usage of host supplied checksum
DELAY	.Equ LOCALS+1		; COMPUTED DELAY FOR TOTAL SEEK

Sv1	.Equ LOCALS+2		; storage during Write16
Sv2	.Equ Sv1+1
Sv3	.Equ Sv1+2
Sv4	.Equ Sv1+3

TEMP1	.Equ Locals+6.		; 2 Locations for temporary by many routines
TEMP2	.Equ TEMP1+1

DatMk1	.Equ Locals+8		; 5 values that indicate start and end of Data field
DatMk2	.Equ DatMk1+1
DatMk3	.Equ DatMk1+2
DatMk4	.Equ DatMk1+3
DatMk5	.Equ DatMk1+4

LOWCNT	.Equ LOCALS+13.		; Holds value for physiacl interleave count
HIHCNT	.Equ LOWCNT+1.		; Same but opposite/complimentary value
CNTPTR	.Equ LOWCNT+2.		; Pointer to which cnt to use ( high or low )
TOTCNT	.Equ LOWCNT+3.		; Total count of sectors written

TEMP3	.Equ Locals+17.
TEMP4	.Equ TEMP3+1

RtyFlg	.Equ Locals+19.		; flag for use in BadAddr error handling
Uu6	.Equ Locals+20.		; 2 unused locations

Cmdx	.Equ Locals+21.
SaveL	.Equ Locals+22.
SaveH	.Equ Locals+23.
CmdLeng	.Equ 3F		; 64 byte ring buffer of 8 byte IOB's
SavIndex	.Equ 80

; *** NOTE -- Ram from 'C0' to 'FF' is used by the 68K as parameter memory ***

LSTUSED	.Equ 0BF		; last used location in the ZERO PARE RAM

.Page
;--
;
;			CONSTANTS
;
;++

BUFR12SZ	.Equ 0B		; LENGTH OF 12 BYTE BLOCK HEADER - 1
NIBLRETR	.Equ 20		; THE NUMBER OF NIBBLES READ SEARCHING FOR THE
			; FIRST ADDRESS MARK DURING A READ
MAXTRACK	.Equ 4F		; MAXIMUM TRACK NUMBER: 79.
MINTRACK	.Equ 0		; MIMIMUM TRACK NUMBER: 0
MAXCLASS	.Equ 04		; Maximum track class value -- range from 0..4
MINSECNT	.Equ 08		; Minimum sector count
MAXSECNT	.Equ 0C		; Maximum sector count
MINSPEED	.Equ 0D4		; Minimum speed value
MAXSPEED	.Equ 038		; Maximum speed value -- Low # = high speed
OkDly	.Equ 28.

CNFMVAL	.Equ 0FF		; Format configuration check byte
LOW6	.Equ 3F		; mask for low 6 bit

MaxCmd	.Equ 09		; 10 commands return FDirH ( -1 )
CmdNumb	.Equ 07		; Seven commands nao accessed through '81'
NullCmd	.Equ 080		; Null/Handshake command
RwtsCmd	.Equ 091		; Read/Write Track/Sector command value
LwCmdNo	.Equ 083		; Lowest command number ( not including '81' )
ClStsCmd	.Equ 085		; Command to clear interrupt status
WrtCmd	.Equ 01		; Value of command to write data to disk
WrtBfCmd	.Equ 08		; Write data, brute force method
FrmtDsk	.Equ 03		; Value of command host to to format disk
VrfyDsk	.Equ 04		; Value of command host to to verify disk
FrmtTrk	.Equ 05		; Value of command from host to format a track
VrfyTrk	.Equ 06		; Value opf command from host to verify a track

ADM1	.Equ 0D5		; Address mark one
ADM2	.Equ 0AA		; Address mark two
ADM3	.Equ 096		; Address mark three
DDM3	.Equ 0AD		; Data mark three

BitSlp1	.Equ 0DE		; Bit slip mark one
BitSlp2	.Equ 0AA		; Bit slip mark two

RclStep	.Equ 4.		; # of steps to take away from Trk00 during recal
OneScc	.Equ 200.		; constant for a one second wait
TmOutRcl	.Equ 100.		; Timeout for recal wait
RdAdrTmt	.Equ 08.		; Tiomeout for looking for address header
IWMMode	.Equ 01F		; constant to setup IWM modes
TurnRound	.Equ 08.		; 5*8=40 msec turn around time for changing directions

Lrge	.Equ 05.
Smal	.Equ 01.
TblJmp	.Equ 09.
WHih	.Equ 17.		; '11' hex
WLow	.Equ 00.
tLow	.Equ 20.

;  ERROR NUMBERS

GErrCmd	.Equ 01		; Gobyte error:  Invalid command
GErrDrv	.Equ 02		; Gobyte error:  Invalid drive number
GErrSid	.Equ 03		; GoByte error:  Invalid side number
GErrSec	.Equ 04		; Gobyte error:  Invalid Sector number
GErrTrk	.Equ 05		; Gobyte error:  Invalid Track number
GErrMsk	.Equ 06		; Gobyte error:  Invalid mask
GErrClm	.Equ 07		; Gobyte error:  No clamped disk in drive
GErrEna	.Equ 08		; Gobyte error:  Drive not enabled
GErrIntr	.Equ 09		; Gobyte error:  Pending interrupts not cleared
GErrFmPr	.Equ 10.		; Gobyte error:  Invalid format parameter

PErrROM	.Equ 11.		; Program error:  ROM test failed
PErrInt	.Equ 12.		; Program error:  Random IRQ, NMI or BRK

DErrCal	.Equ 13.		; Drive error:  time out while looking for track zero
IWMError	.Equ 14.		; Fatal error:  IWM doesn't respond to commands
StepErr	.Equ 15.		; Handshake diod not occur when stepping
DErrTk0	.Equ 16.		; Drive Error:  Unable to leave track zero location

SErrProt	.Equ 20.		; Errstat error:  Write protect error
SErrFrmt	.Equ 21.		; Errstat error:  Can't verify disk
SErrClmp	.Equ 22.		; Errstat error:  Unable to clamp disk
SErrRd	.Equ 23.		; Errstat error:  Read error
SErrWr	.Equ 24.		; Errstat error:  Write error
SErrUclmp	.Equ 25.		; Errstat error:  Unable to unclamp diskette
SErrNoA9	.Equ 26.		; Errstat error:  Cannot find A9's during chkspd
SErrTmt	.Equ 27.		; Errstat error:  Unable to adjust speed w/in timeout
SErrM1Tk	.Equ 28.		; Errstat error:  Cannot write speed track

ErrHdr	.Equ 30.		; UnderRun while writing header
ErrWrt	.Equ 31.		; UnderRun while writing data fields

.Page
;++
;
;		Data Buffer equates and Bad Block equates
;
;--

StackSt	.Equ 0CF		; Init stack to "01CF" -- push down stack
SctrCnt	.Equ 01D0		; During VERIFY, will no. of bad sectors
TrkNumb	.Equ SctrCnt+1		; Track number where bad sector occurred
SidNumb	.Equ SctrCnt+2		; Side number where bad sector occurred
SctrSav	.Equ SctrCnt+3		; Start of buffer where sector numbers are saved

Page01	.Equ 100		; last 12 bytes of data are for read/write
Bufr12	.Equ 1F4		; last 12 bytes of data for raed/write
Page02	.Equ 200		; 256 bytes of data for read/write
Page03	.Equ 300		;  "

Pg2Len	.Equ 0FF		; # of bytes to read during Wrbf02 loop
Pg3Len	.Equ 0FE		; # of bytes to read during Wrbf03 loop

.Page

;--
;		I/O Space
;++

IOSpace	.Equ 800		; name for beginning of I/O space offsets
Off	.Equ 00		; Offset to switch a phase off
On	.Equ 01		; Offset to switch a phase on
Zero	.Equ 00		; Offset to drive zero
Eighty	.Equ 01		; Offset to drive eighty
Low	.Equ 00		; PwmEna + Low enables output of PWMReg
High	.Equ 01
InWard	.Equ 00		; direction offsets
OutWard	.Equ 01

CA0	.Equ IOSpace		; Control signal 0 for MCI PAL in Sony drive
CA1	.Equ IOSpace+2		; signal 1
CA2	.Equ IOSpace+4		; signal 2
LStrb	.Equ IOSpace+6		; Load strobe -- 0 to 1 to 0 will strobe PAL

MtEna	.Equ IOSpace+8		; Enables output of DrvEna

DrEna	.Equ IOSpace+10.	; = 0 --> drive 0, = 1 ==> drive 80

Q6L	.Equ IOSpace+12.	; Low = Read or Write
Q6H	.Equ Q6L+1		; High = Sense or Write Load
Q7L	.Equ IOSpace+14.	; Low disables writing to disk
Q7H	.Equ Q7L+1		; Enables /WrReq output of IWM

CntEna	.Equ IOSpace+16.	; low enables PWM counter/comparator

PwmEna	.Equ IOSpace+22.	; High enables pulses to Sony, else always low

DisL	.Equ IOSpace+24.	; Memory enable for the 68K
DisH	.Equ DisL+1		; Memory disable for the 68K

Side0Sel	.Equ IOSpace+26.	; Selects side 0
Side1Sel	.Equ Side0Sel+1		; Selects side 1

BootL	.Equ IOSpace+28.	; Disk Diag Line; when High then I'm listening
BootH	.Equ BootL+1

FDirL	.Equ IOSpace+30.	; Deselects the interrupts to the 68K
FDirH	.Equ FDirL+1		; Selects the interrupts to the 68K

PWMReg	.Equ IOSpace+32.	; Selects the PWM register for writing

;
Home Documents Lisa TTKCLASS.Text
TTKCLASS.Text

TTKCLASS.Text

Lisa · TEXT
FilenameTTKCLASS.Text
Size0.00 MB
Subsection firmware / ROM88
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Contents
.Page
;++
;			TrackClass will return the class (from 0 to 8) of
;		the track in IIOB+Track in the "Y" register
;
;		returns:		"Y" reg = class of track
;					"A" reg = IIOB+Track
;					"X" reg = unchanged
;--

TrkClss	.Equ *				; Entry point
	Lda	IIOB+Track		; Fetch current track value
	Ldy	#MaxClass		; Maximum class value
$21	Cmp	ClssTbl,Y		; Track >= Table entry?
	Bcs	$42			; Yep
	Dey
	Bne	$21			; Try the next track class
$42	Rts				; "Y" reg = track class value


ClssTbl	.Equ *				; Start of track class table
	.Byte 00			; Track  0:15
	.Byte 10			; Track 16:31
	.Byte 20			; Track 32:47
	.Byte 30			; Track 48:63
	.Byte 40			; Track 64:79
Home Documents Macintosh Mac Technical Notes.Html
Mac Technical Notes.Html

Mac Technical Notes.Html

Macintosh · HTML
FilenameMac_Technical_Notes.html
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Contents
<h1 class="sectionedit1" id="mac_technical_notes">Mac Technical Notes</h1>
<div class="level1">

<p>
Compiled from many sources including Linux and NetBSD kernel source, 
Guide to the Macintosh Family Hardware 1st and 2nd editions, Designing 
Cards and Drivers for the Macintosh Family 3rd edition, <a href="http://web.archive.org/web/20100729100247/http://developer.apple.com/legacy/mac/library/documentation/Hardware/hardware2.html" class="urlextern" title="http://web.archive.org/web/20100729100247/http://developer.apple.com/legacy/mac/library/documentation/Hardware/hardware2.html" rel="nofollow">Apple hardware notes (archive)</a>, even <a href="http://developer.apple.com/legacy/library/navigation/index.html" class="urlextern" title="http://developer.apple.com/legacy/library/navigation/index.html" rel="nofollow">more Apple hardware notes</a>, and good old fashioned reverse-engineering.
</p>

<p>
This concentrates mostly on Mac II and later machines since the 
Plus/SE/Classic are fairly well understood. Please contact messdrivers 
[at] gmail [dot] com if you have any further information on any Mac 
models.
</p>
<hr>

</div>

<h1 class="sectionedit2" id="basic_memory_map">Basic Memory Map</h1>
<div class="level1">

<p>
On most Mac II and later machines, it's like this:
</p>
<ul>
<li class="level1"><div class="li"> 0x00000000-0x3fffffff = RAM</div>
</li>
<li class="level1"><div class="li"> 0x40000000-0x4fffffff = ROM</div>
</li>
<li class="level1"><div class="li"> 0x50000000-0x5fffffff = I/O</div>
</li>
<li class="level1"><div class="li"> 0x60000000-0xefffffff = NuBus “super slot” space</div>
</li>
<li class="level1"><div class="li"> 0xf1000000-0xffffffff = NuBus “standard slot” space</div>
</li>
</ul>
<ul>
<li class="level1"><div class="li"> 0xfe000000 = VRAM (SE/30 only)</div>
</li>
<li class="level1"><div class="li"> 0xfeff0000 = VROM (SE/30) (note that
 while the main ROM has a valid driver at the end, SE/30 has a separate 
64 kbit VROM on the board which I dumped. The actual driver is very 
small, it contains mostly hardware credits for the SE/30)</div>
</li>
</ul>

<p>
Note that Macs with on board video except for the SE/30 typically 
contain one or more valid video drivers in ROM; the correct one is used 
when the machine type is identified.
</p>

<p>
I/O devices are given as offsets from 0x50000000. Each device is mapped across 0x2000 bytes unless noted otherwise.
</p>
<ul>
<li class="level1"><div class="li"> VIA1 at offset 0. May also be mirrored at 0x20000 and 0x40000.</div>
</li>
<li class="level1"><div class="li"> VIA2 at offset 0x2000 on II, IIx, IIcx, and SE/30</div>
</li>
<li class="level1"><div class="li"> SCC (Z8530) at offset 0x4000</div>
</li>
<li class="level1"><div class="li"> SCSI (pseudo-DMA w/DRQ on II, handshake on SE/30) at offset 0x6000</div>
</li>
<li class="level1"><div class="li"> SCSI (normal) at 0x10000</div>
</li>
<li class="level1"><div class="li"> SCSI (pseudo-DMA, no DRQ) at offset 0x12000</div>
</li>
<li class="level1"><div class="li"> ASC (Apple Sound Chip) at 0x14000</div>
</li>
<li class="level1"><div class="li"> IWM/SWIM (floppy) at 0x16000</div>
</li>
</ul>
<ul>
<li class="level1"><div class="li"> VDAC (palette) at 0x24000 (IIci, IIsi, LC series, Color Classic)</div>
</li>
<li class="level1"><div class="li"> RBV/V8/etc registers (partially emulates VIA2, also video registers) at 0x26000 (IIci &amp; IIsi, LC series, Color Classic)</div>
</li>
<li class="level1"><div class="li"> RBV VRAM at 0x1000000 (IIci)</div>
</li>
</ul>

<p>
The entire I/O space mirrors every 0x20000 on Mac II, IIx, IIcx, and 
SE/30. IIsi and IIfx mirror every 0x40000. IIci and Color Classic (and 
LC series?) do not mirror. The ROMs use this mirroring behavior along 
with other markers to determine the model they're running on.
</p>

<p>
The bottom 8k or so of RAM contains significant system data on these Macs. See <a href="http://www.osdata.com/system/physical/lowmem.htm#Mac" class="urlextern" title="http://www.osdata.com/system/physical/lowmem.htm#Mac" rel="nofollow">Low Memory Globals</a> and <a href="http://www.mac.linux-m68k.org/devel/macalmanac.php" class="urlextern" title="http://www.mac.linux-m68k.org/devel/macalmanac.php" rel="nofollow">Mac Almanac</a>
 for lists. Note that on the IIci/IIsi the video frame buffer is at 
physical address 0; the 68030 MMU is used to remap addresses so software
 sees address 0 elsewhere and thus the low-memory globals work as usual.
</p>
<hr>

</div>

<h1 class="sectionedit3" id="via_1">VIA 1</h1>
<div class="level1">

<p>
Data register A for the Mac 128/512/512e/Plus
</p>
<ul>
<li class="level1"><div class="li"> bit 7 = SCC Wait/Request input</div>
</li>
<li class="level1"><div class="li"> bit 6 = Alternate screen buffer output</div>
</li>
<li class="level1"><div class="li"> bit 5 = Floppy disk head select output</div>
</li>
<li class="level1"><div class="li"> bit 4 = output: overlay ROM at 0 when 1 (enabled at reset)</div>
</li>
<li class="level1"><div class="li"> bit 3 = Alternate sound buffer output</div>
</li>
<li class="level1"><div class="li"> bits 0-2 = Sound volume output</div>
</li>
</ul>

<p>
On the SE, bit 4 changes to select upper/lower internal floppy drive 
(the ROM overlay is enabled at reset and disabled by the first 
instruction fetch at 0x4xxxxx).
</p>

<p>
Data register A for the SE/30, II, IIx, and IIcx:
</p>
<ul>
<li class="level1"><div class="li"> bit 7 = SCC Wait/Request input</div>
</li>
<li class="level1"><div class="li"> bit 6 = Alternate screen buffer output on SE/30, model number input on others</div>
</li>
<li class="level1"><div class="li"> bit 5 = Floppy disk head select output</div>
</li>
<li class="level1"><div class="li"> bit 4 = output: overlay ROM at 0 when 1 (enabled at reset)</div>
</li>
<li class="level1"><div class="li"> bit 3 = output: 1 to enable synchronous modem support on port A</div>
</li>
<li class="level1"><div class="li"> bits 0-2 = reserved (bit 0 must be 1 to avoid forced diagnostic boot over AppleTalk)</div>
</li>
</ul>

<p>
Data register A for the IIci / IIfx:
</p>
<ul>
<li class="level1"><div class="li"> bit 7 = SCC Wait/Request input</div>
</li>
<li class="level1"><div class="li"> bit 6 = model ID bit 3 (1 for IIci or IIfx)</div>
</li>
<li class="level1"><div class="li"> bit 5 = Floppy disk head select output</div>
</li>
<li class="level1"><div class="li"> bit 4 = model ID bit 2 (1 for IIfx or IIci with parity option)</div>
</li>
<li class="level1"><div class="li"> bit 3 = output: 1 to enable synchronous modem support on port A</div>
</li>
<li class="level1"><div class="li"> bit 2 = model ID bit 1 (1 for IIci, 0 for IIfx)</div>
</li>
<li class="level1"><div class="li"> bit 1 = model ID bit 0 (1 for IIci or IIfx)</div>
</li>
<li class="level1"><div class="li"> bit 0 = reserved (must be 1 to avoid forced diagnostic boot over AppleTalk)</div>
</li>
</ul>

<p>
Data register B for the Mac 128/512/512e/Plus:
</p>
<ul>
<li class="level1"><div class="li"> bit 7 = output: 0 to enable sound, 1 to disable</div>
</li>
<li class="level1"><div class="li"> bit 6 = input: 0 = video in display portion of scanline, 1 = hblank or vblank</div>
</li>
<li class="level1"><div class="li"> bit 5 = input: mouse Y2</div>
</li>
<li class="level1"><div class="li"> bit 4 = input: mouse X2</div>
</li>
<li class="level1"><div class="li"> bit 3 = input: mouse button (0 = pressed)</div>
</li>
<li class="level1"><div class="li"> bit 2 = output: 0 = enable RTC chip select</div>
</li>
<li class="level1"><div class="li"> bit 1 = output: RTC clock line</div>
</li>
<li class="level1"><div class="li"> bit 0 = output: RTC data line</div>
</li>
</ul>

<p>
Data register B in the SE/30, II, IIx, IIfx, IIcx, and IIci:
</p>
<ul>
<li class="level1"><div class="li"> bit 7 = input on IIci (parity error), output otherwise (sound enable, but ignored by h/w)</div>
</li>
<li class="level1"><div class="li"> bit 6 = output: 0 to enable parity checking on IIci, 0 to enable vsync IRQ on SE/30, unused otherwise</div>
</li>
<li class="level1"><div class="li"> bit 5 = output: ADB state 1 (except IIfx)</div>
</li>
<li class="level1"><div class="li"> bit 4 = output: ADB state 0 (except IIfx)</div>
</li>
<li class="level1"><div class="li"> bit 3 = input: ADB interrupt (except IIfx)</div>
</li>
<li class="level1"><div class="li"> bit 2 = output: 0 = enable RTC chip select</div>
</li>
<li class="level1"><div class="li"> bit 1 = output: RTC clock line</div>
</li>
<li class="level1"><div class="li"> bit 0 = output: RTC data line</div>
</li>
</ul>
<hr>

</div>

<h1 class="sectionedit4" id="via_2">VIA 2</h1>
<div class="level1">
<hr>

</div>

<h1 class="sectionedit5" id="coprocessors">Coprocessors</h1>
<div class="level1">

<p>
Separate pages are in progress discussing technical features of each of 
the co-processors used on various Macs. These typically handle ADB, 
clock, and PRAM, plus power management features on portables and power 
on/off on some desktops.
</p>

<p>
<a href="http://mess.redump.net/mess/driver_info/m50753-based_pmu" class="wikilink1" title="mess:driver_info:m50753-based_pmu">M50753 PMUs</a> (Mac Portable, PowerBook 100, 140/170, 145(B), 160/180)
</p>

<p>
68HC05-based PMU (PowerBook 150, 190, all Duos, 5xx)
</p>

<p>
<a href="http://mess.redump.net/mess/driver_info/68hc05-based_egret" class="wikilink2" title="mess:driver_info:68hc05-based_egret" rel="nofollow">68HC05-based Egret</a>
 (LC, LC II, LC III, Classic II, IIsi, IIvx/IIvi), Caboose (some 
Quadras), and Cuda (Color Classic, most 68040 machines, all PowerPC 601,
 603, 604, and most G3).
</p>
<hr>

</div>

<h1 class="sectionedit6" id="hardware_ids">Hardware IDs</h1>
<div class="level1">

<p>
There are 3 ID schemes used on the various 68020/030/040 Macs. The first
 uses bit 6 of port A on VIA1 (PA6) and bit 3 of port B on VIA 2 (PB3) 
and works like this:
</p>
<div class="table sectionedit7"><table class="inline">
	<thead>
	<tr class="row0">
		<th class="col0 leftalign"> Model    </th><th class="col1">PA6 </th><th class="col2">PB3 </th>
	</tr>
	</thead>
	<tbody><tr class="row1">
		<td class="col0 leftalign"> Mac IIx  </td><td class="col1 leftalign">0   </td><td class="col2 leftalign">0   </td>
	</tr>
	<tr class="row2">
		<td class="col0 leftalign"> Mac II   </td><td class="col1 leftalign">0   </td><td class="col2 leftalign">1   </td>
	</tr>
	<tr class="row3">
		<td class="col0"> Mac SE/30</td><td class="col1 leftalign">1   </td><td class="col2 leftalign">0   </td>
	</tr>
	<tr class="row4">
		<td class="col0"> Mac IIcx </td><td class="col1 leftalign">1   </td><td class="col2 leftalign">1   </td>
	</tr>
</tbody></table></div>

<p>
The second uses 4 bits in VIA1 port A: bits 6, 4, 2, and 1 (PA6, PA4, PA2, and PA1, respectively).
</p>

<p>
This second scheme is further indexed by the core ASIC type detected by 
the Universal ROM. The PowerBook 170 and Classic II have the same ID 
bits, but that works because the PB170 and Classic II have very 
different core ASICs that are easily detected as different. These bits 
also are used to differentiate machines with the same ID word such as 
the Quadra and Centris 610/650/800.
</p>
<div class="table sectionedit8"><table class="inline">
	<thead>
	<tr class="row0">
		<th class="col0 leftalign">Model                  </th><th class="col1">PA6</th><th class="col2">PA4</th><th class="col3">PA2</th><th class="col4">PA1</th>
	</tr>
	</thead>
	<tbody><tr class="row1">
		<td class="col0 leftalign">PowerBook 150          </td><td class="col1 leftalign">0  </td><td class="col2 leftalign">0  </td><td class="col3 leftalign">0  </td><td class="col4 leftalign">0  </td>
	</tr>
	<tr class="row2">
		<td class="col0 leftalign">Color Classic          </td><td class="col1 leftalign">0  </td><td class="col2 leftalign">0  </td><td class="col3 leftalign">0  </td><td class="col4 leftalign">1  </td>
	</tr>
	<tr class="row3">
		<td class="col0 leftalign">Unused                 </td><td class="col1 leftalign">0  </td><td class="col2 leftalign">0  </td><td class="col3 leftalign">1  </td><td class="col4 leftalign">0  </td>
	</tr>
	<tr class="row4">
		<td class="col0">Unreleased MDU-using SE/30 Successor</td><td class="col1">0</td><td class="col2">0</td><td class="col3">1</td><td class="col4">1</td>
	</tr>
	<tr class="row5">
		<td class="col0 leftalign">Quadra 950             </td><td class="col1 leftalign">0  </td><td class="col2 leftalign">1  </td><td class="col3 leftalign">0  </td><td class="col4 leftalign">0  </td>
	</tr>
	<tr class="row6">
		<td class="col0">PowerBook 140/170, Classic II, Quadra 800</td><td class="col1">0</td><td class="col2">1</td><td class="col3">0</td><td class="col4">1</td>
	</tr>
	<tr class="row7">
		<td class="col0 leftalign">Used, unknown machine  </td><td class="col1 leftalign">0  </td><td class="col2 leftalign">1  </td><td class="col3 leftalign">1  </td><td class="col4 leftalign">0  </td>
	</tr>
	<tr class="row8">
		<td class="col0 leftalign">Mac IIsi               </td><td class="col1 leftalign">0  </td><td class="col2 leftalign">1  </td><td class="col3 leftalign">1  </td><td class="col4 leftalign">1  </td>
	</tr>
	<tr class="row9">
		<td class="col0">Quadra 700, Centris 610</td><td class="col1 leftalign">1  </td><td class="col2 leftalign">0  </td><td class="col3 leftalign">0  </td><td class="col4 leftalign">0  </td>
	</tr>
	<tr class="row10">
		<td class="col0 leftalign">Unreleased 20Mhz 650   </td><td class="col1 leftalign">1  </td><td class="col2 leftalign">0  </td><td class="col3 leftalign">0  </td><td class="col4 leftalign">1  </td>
	</tr>
	<tr class="row11">
		<td class="col0 leftalign">Quadra 610             </td><td class="col1 leftalign">1  </td><td class="col2 leftalign">0  </td><td class="col3 leftalign">1  </td><td class="col4 leftalign">0  </td>
	</tr>
	<tr class="row12">
		<td class="col0 leftalign">Mac IIci, Centris (25Mhz) 650  </td><td class="col1 leftalign">1  </td><td class="col2 leftalign">0  </td><td class="col3 leftalign">1  </td><td class="col4 leftalign">1  </td>
	</tr>
	<tr class="row13">
		<td class="col0 leftalign">Quadra 900             </td><td class="col1 leftalign">1  </td><td class="col2 leftalign">1  </td><td class="col3 leftalign">0  </td><td class="col4 leftalign">0  </td>
	</tr>
	<tr class="row14">
		<td class="col0 leftalign">Mac IIfx, Quadra (33Mhz) 650   </td><td class="col1 leftalign">1  </td><td class="col2 leftalign">1  </td><td class="col3 leftalign">0  </td><td class="col4 leftalign">1  </td>
	</tr>
	<tr class="row15">
		<td class="col0">Mac LC, LC2, IIvx, IIvi</td><td class="col1 leftalign">1  </td><td class="col2 leftalign">1  </td><td class="col3 leftalign">1  </td><td class="col4 leftalign">0  </td>
	</tr>
	<tr class="row16">
		<td class="col0 leftalign">Mac IIci w/PGC         </td><td class="col1 leftalign">1  </td><td class="col2 leftalign">1  </td><td class="col3 leftalign">1  </td><td class="col4 leftalign">1  </td>
	</tr>
</tbody></table></div>

<p>
The third and most scalable is a machine ID register at 0x5ffffffc. The 
top word must be 0xa55a to be valid. Then bits 15-11 are 0 for consumer 
Macs, 1 for portables, 2 for high-end 68k, and 3 for high-end PowerPC. 
Bit 10 is 1 if additional ID bits appear elsewhere (e.g. in VIA1). The 
rest of the bits are a per-model identifier. Updated and corrected 
January 2, 2012: confusion between “Blackbird” the IIfx codename and 
“Blackbird” the PowerBook 5×0 codename resolved, and many new ID values 
added on through the end of the Old World.
</p>
<div class="table sectionedit9"><table class="inline">
	<thead>
	<tr class="row0">
		<th class="col0 leftalign">Model               </th><th class="col1">Lower 16 bits of ID</th>
	</tr>
	</thead>
	<tbody><tr class="row1">
		<td class="col0 leftalign">LC III              </td><td class="col1">0x0001</td>
	</tr>
	<tr class="row2">
		<td class="col0 leftalign">LC III+             </td><td class="col1">0x0003</td>
	</tr>
	<tr class="row3">
		<td class="col0 leftalign">LC 520              </td><td class="col1">0x0100</td>
	</tr>
	<tr class="row4">
		<td class="col0">LC 550 (and Color Classic II?)</td><td class="col1">0x0101</td>
	</tr>
	<tr class="row5">
		<td class="col0 leftalign">PowerBook Duo 280c  </td><td class="col1">0x1000</td>
	</tr>
	<tr class="row6">
		<td class="col0 leftalign">PowerBook Duo 270c  </td><td class="col1">0x1002</td>
	</tr>
	<tr class="row7">
		<td class="col0 leftalign">PowerBook Duo 210   </td><td class="col1">0x1004</td>
	</tr>
	<tr class="row8">
		<td class="col0 leftalign">PowerBook Duo 230   </td><td class="col1">0x1005</td>
	</tr>
	<tr class="row9">
		<td class="col0 leftalign">PowerBook Duo 235   </td><td class="col1">0x1006</td>
	</tr>
	<tr class="row10">
		<td class="col0 leftalign">PowerBook 520/540   </td><td class="col1">0x1808</td>
	</tr>
	<tr class="row11">
		<td class="col0 leftalign">PowerBook Duo 2300  </td><td class="col1">0x1809</td>
	</tr>
	<tr class="row12">
		<td class="col0 leftalign">PowerBook 5300      </td><td class="col1">0x180a</td>
	</tr>
	<tr class="row13">
		<td class="col0 leftalign">PowerBook 190       </td><td class="col1">0x180b</td>
	</tr>
	<tr class="row14">
		<td class="col0 leftalign">IIvx                </td><td class="col1">0x2015</td>
	</tr>
	<tr class="row15">
		<td class="col0 leftalign">LC 475              </td><td class="col1">0x2221</td>
	</tr>
	<tr class="row16">
		<td class="col0 leftalign">Quadra 605          </td><td class="col1">0x2225</td>
	</tr>
	<tr class="row17">
		<td class="col0 leftalign">Quadra 630          </td><td class="col1">0x2226</td>
	</tr>
	<tr class="row18">
		<td class="col0 leftalign">LC 575              </td><td class="col1">0x222e</td>
	</tr>
	<tr class="row19">
		<td class="col0">Quadra/Centris 610/650/800</td><td class="col1">0x2BAD</td>
	</tr>
	<tr class="row20">
		<td class="col0 leftalign">Quadra 660/840      </td><td class="col1">0x2830</td>
	</tr>
	<tr class="row21">
		<td class="col0 leftalign">PowerMac 6100       </td><td class="col1">0x3010</td>
	</tr>
	<tr class="row22">
		<td class="col0 leftalign">PowerMac 7100       </td><td class="col1">0x3012</td>
	</tr>
	<tr class="row23">
		<td class="col0 leftalign">PowerMac 8100       </td><td class="col1">0x3013</td>
	</tr>
	<tr class="row24">
		<td class="col0 leftalign">PowerMac 7500       </td><td class="col1">0x3020</td>
	</tr>
	<tr class="row25">
		<td class="col0 leftalign">PowerMac 7300       </td><td class="col1">0x3021</td>
	</tr>
	<tr class="row26">
		<td class="col0">PowerMac 7600/8600/9600</td><td class="col1">0x3022</td>
	</tr>
	<tr class="row27">
		<td class="col0 leftalign">PowerBook 2400      </td><td class="col1">0x3025</td>
	</tr>
	<tr class="row28">
		<td class="col0 leftalign">PowerBook 3400      </td><td class="col1">0x3026</td>
	</tr>
	<tr class="row29">
		<td class="col0">PowerMac G3 “Beige” </td><td class="col1">0x3041</td>
	</tr>
	<tr class="row30">
		<td class="col0">PowerBook G3 “WallStreet”</td><td class="col1">0x3042</td>
	</tr>
	<tr class="row31">
		<td class="col0">PowerBook G3 “WallStreet”</td><td class="col1">0x3046</td>
	</tr>
	<tr class="row32">
		<td class="col0 leftalign">Pippin @Mark        </td><td class="col1">0x7100</td>
	</tr>
</tbody></table></div>

</div>

<h1 class="sectionedit10" id="known_non-_new_world_roms">Known non-"New World" ROMs</h1>
<div class="level1">

<p>
All Mac ROMs contain a checksum in the first 4 bytes of the image. This 
is what the “Apple checksum” below is referring to, and not the CRC32 of
 the entire file. The Apple checksum is calculated by taking the low 32 
bits of the sum of every unsigned 16 bit word in the rom, except for the
 first 4 bytes.
</p>

<p>
“Release date” is sometimes the ROM's internal release date rather than when the system was introduced to the public.
</p>

<p>
“Major Version” is the word at offset 0x8. “Minor Version” is the word at offset 0x12. “Sub Release” is the word at offset 0x4c.
</p>
<div class="table sectionedit11"><table class="inline">
	<thead>
	<tr class="row0">
		<th class="col0">S…

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