# PowerKey Rebound!

This document contains experimentally-observed behavior of the ADB protocol of the Sophisticated Circuits PowerKey Rebound! (PKRB-M). It contains enough information to satisfactorally emulate the device, however, a few unknowns exist.

The Rebound!'s default address is 0x7 and its default handler ID is 0x87.

## ADB Registers

The Rebound! has eight registers that are accessed using ADB registers 1 and 2.  ADB register 1 controls which Rebound! register is reflected in ADB register 2 - Listen 2 will set the contents of the register, Talk 2 will read the contents of the register.

## Rebound! Registers

### Register 0

16 bits in length, purpose unknown, default value 0x0102.  Version 1.1 of the software does not read it.

### Register 1

16 bits in length, purpose unknown, default value 0x1000.  Version 1.1 of the software reads it when the extension is loaded.

### Register 2

32 bits in length, contains the serial number of the Rebound! dongle.  Version 1.1 of the software reads it when the extension is loaded.

### Registers 3-5

Register 3 is 16 bits in length and contains a counter which decrements by 1 once per second.  When it reaches 0, if register 5 is nonzero, register 5 is decremented, register 3 is set to the value in register 4, and the Mac is restarted by a Cmd-Ctrl-Reset keystroke emulated on the keyboard.  If register 5 is zero when register 3 decrements to zero, registers 3 and 5 remain at zero and the Mac is not restarted.

Version 1.1 of the software, by default, sets registers 3 and 4 to 0x11E (286) and register 5 to 1, then sets register 3 to 0x11E once per minute.

### Register 6

16 bits in length, purpose unknown, default value 0x0000.  Version 1.1 of the software does not read it.

### Register 7

16 bits in length, purpose unknown, default value 0x0000.  Version 1.1 of the software does not read it.

.Page
;++
;--

TimIt	.Equ *
	Lda	#5				; Time 6 pulses
	Sta	Temp2
	Clc					; Should stay clear unless explicitly set
	Jsr	WtZero				; Look for low, then first high
	Bcs	RsOut				; 2,3	10	No edge within timeout period
	Jsr	RsEdge				; 8	8	Now at known locationo
	Bcs	RsOut				; 2,3	10	No edge within timeout period
	Lda	#0				; 2	12
	Sta	RangeL				; 3	15
	Sta	RangeH				; 3	18	Zero both bytes of counter

;++
;	WtZero & RsEdge both have 36 cycles (18.0 uSec) per tick of RangeL:H
;--

$20	Jsr	WtZero				; Look for low
	Bcs	RsOut				; 2,3
	Jsr	RsEdge				; Wait for next edge on pulse
	Bcs	RsOut				; 2,3
	Dec	Temp2				; 5		When less than zero then exit
	Bpl	$20				; 2,3	15*(2+@+%+#) = 180 cycles

RsOut	.Equ *
	Rts					; 6		Common exit point

WtZero	.Equ *
	Bit	K000				; 3		ccV set to Zero
	Bvc	RsEd				; 3	6

RsEdge	.Equ *					;		Look for a rising edge
	Bit	K0FF				; 3	3	ccV eq 0 == low, ccV eq 1 == high
	Bvs	ReEd				; 3	6
RsEd	.Equ *
	Ldy	#00				; 2	8
	Ldx	#0A0				; 2	10	Constant timeout for pulse counting

$10	Dey					; 2	2
	Bne	$20				; 2,3	4,5
	Dex					; 2	6
	Bne	$30				; 2,3	8,9
	Sec					; 2	10	When X-reg = 0 then return error
	Rts

$20	Nop					; 2	7
	Nop					; 2	9	Waste time

$30	Inc	RangeL				; 5	14
	Bne	$40				; 2,3	16,17
	Inc	RangeH				; 5	21
	Bne	$50				; 3	24	Always taken ??

$40	Pha					; 3	20	Waste more time
	Pla					; 4	24

$50	Lda	Q7L				; 4		Bit7=0 ==>tach low, else tach high
	Bvc	$70				; 2,3	30,31	ccV ==> look for low
	Bpl	$90				; 2,3	32,33	If high then fall thru & exit
	Nop					; 2	34
$60	Rts					; 6

$70	Bpl	$60				; 2,3	33,34	If low then exit

$90	Bcc	$10				; 3	36	Always taken?? -- 18.0 uSec loop

ChkLrg	.Equ *
	Lda	#Lrge				; 5
	Sta	Temp1				; For speed adjustment
	Lda	#WLow
	Beq	ChkComm

ChkSml	.Equ *
	Lda	#Smal				; 1
	Sta	Temp1
	Lda	#TLow

;++
;  ChkComm
;     if H < TL
;       then AdjPlus
;     else if H > TL
;       then TstHih
;     else  if L < Tl
;       then AdjPlus
;     else if L = TL
;       then OK
;  TstHih
;     If H > Th
;        then AdjMinus
;     else if H <> Th
;        then OK
;     else if L <= TH
;        then OK
;     else AdjMinus
;--

ChkComm	.Equ *
	Sta	InxPtrL			; Ptr to which constraints ( low of high )
	Lda	CurClass			; Current track class
	Asl	A			; *2 to address word array
	Tay
	Lda	RangeH
	Cmp	@InxPtrL,y		; High must be greater than or equal to lowtable,y
	Bcc	AdjPlus			; High byte low, must spin slower
	Bne	TsHih			; High byte greater -- must see if w/in high boundary
	Inc
	Lda	RangeL
	Cmp	@InxPtrL,y		; Must be greater than or equal to table,y
	Bcc	AdjPlus			; High bytes = and low byte low - slow it down
	Beq	ChkOK			; Both bytes are equal so within range
	Clc
TsHih	.Equ *				; ccC=1 if branched to here so add +1 for not 'Iny'
	Tya
	Adc	#TblJmp			; 9.
	Tay				; Index now points at high side of range
	Lda	@InxPtrL,y
	Cmp	RangeH			; High byte must be <= high boundary
	Bcc	AdjMinus			; High byte is too high, spin disk faster
	Bne	ChkOK			; If <> then low byte must be w/in range
	Iny				; Point @ low byte of boundary value
	Lda	@InxPtrL,y
	Cmp	RangeL			; Low byte is too high, spin disk faster

ChjkOK	.Equ *
	Clc
	Rts

AdjPlus	.Equ *				; ccC = 0 already
	Ldy	CurClass
	Lda	MSpdTbl,y
	Adc	TEmp1			; Add adjustment value
	Sta	MSpdTbl,y
	Sec
	Rts

AdjMinus	.Equ *
	Ldy	CurClass
	Lda	MSpdTbl,y
	Sec
	Sbc	Temp1
	Sta	MSpdTbl,y
	Sec
	Rts

SpdChk	.Equ *				; Main entry point for speed check
	Lda	#WHih			; '11'x
	Sta	InxPtrH
	Jsr	SetTach			; Make sure in Tach sense mode
	Jsr	TimIt			; Time 6 pulses & abort on timeout
	Bcs	SpdErr
	Jsr	ChkLrg			; Must be within +/- 2%
	Bcc	SpdDone
	Lda	#101.			; 100 times total for attempts to adjust
	Sta	Counter

$10	Dec	Counter
	Beq	SpdErr			; Try for 100 times and abort upon inability to adjust
	Jsr	SetSpeed
	Lda	ScDly
	Jsr	Wait
	Jsr	Timit
	Bcs	SpdErr
	Jsr	ChkLrg
	Bcs	$10			; Loop until speed within +/- 2%

$32	Sec				; Make sure error flag is set
	Dec	Counter
	Beq	SpdErr			; Try for 100 times and abort upon inability to adjust
	Jsr	ChkSml			; Now loop until within +/- .5%
	Bcc	SpdDone
	Jsr	SetSpeed
	Lda	ScDelay
	Jsr	Wait
	Jsr	TimIt
	Bcc	$32

SpdErr	.Equ*
	Lda	#SErrTmt

SpdDone	.Equ *
	Rts

.Page
;++
;
;		VfyCksum -- Verify checksum that was just read.
;
; VfyCksum will undo the mess that CreCksum created by xor'ing the
; checksum into the data bytes.  See teh CreCksum description for the
; alogrithm used to understand what is being undone here.
;
; REGISTERS
;  IN
;	All =	Any value
;  OUT
;	All =	Destroyed
;	ccC =	0 if checksum matches
;		1 if checksum does not match
;
; CALLS
;	NONE
;
;--
VfyCksum	.Equ *				; Entry point for all callers
	Lda	#00			; Init temporary checksums to zero
	Sta	TCksm1
	Sta	TCksm2
	Sta	InxPtrl
	Sta	InxPtrH
	Inc	InxPtrH			; Start at page 1
	Ldy	#0F4			; Only last 12 bytes

VfTop	.Equ *
	Asl	A			; Rotate the third checksum byte
	Php				; Save the status bits
	Adc	#00			; Put carry bit into low bit (8 bit rotate)
	Sta	TCksm3			; Save 3rd checksum byte
	Plp				; Restore status bits
	Lda	@InxPtrL,y		; Read 1st byte of 3 byte loop
	Eor	TCksm3			; restore original data
	Sta	@InxPtrL,y
	Adc	TCksm1
	Sta	TCksm1			; And update the checksum
	Iny
	Bne	$20
	Inc	InxPtrH			; Next page

$20	Lda	@InxPtrL,y		; 2nd of 3 byte loop
	Eor	TCksm1			; Restore originl data
	Sta	@InxPtrL,y
	Adc	TCksm2
	Sta	TCksm2			; And update the checksum
	Iny
	Beq	$60			; Last byte to sum

	Lda	@InxPtrL,y		; 3rd byte of 3 byte loop
	Eor	TCksm2			; Restore original data
	Sta	@InxPtrL,y
	Adc	TckSm3			; Update checksum and leave in A
	Iny
	Bne	VfTop			; Not at page boundary, loop
	Inc	InxPtrH			; Next page
	Bne	VfTop			; Branch always taken

$60	Cmp	CkSm2			; 'A' reg has TCksm2
	Bne	$80
	Lda	TCksm3
	Cmp	Cksum3
	Bne	$80
	Lda	TCksm1
	Cmp	Cksum1
	Bne	$80
	Clc
	Rts

$80	Sec
	Rts

.Page
;++
;	Write16
;
; $10	Ldx	Q6L	; 1	1	Assume worst case
;	Bpl	$10	; 3	4	branch taken
;	Ldx	Q6L	; 4	8	bit will be set
;	Bpl	$10	; 2	10	fall thru
;	Sta	Q6H	; 4	14	put the data into reg
; 31 cycles max after bit is set before UnderRun bit is set.  Using above code
; as start of time critical code,
; total time = ((32-14)+31) = 49 cycles
;--
.Page
	.Org	1A00
Write16	.Equ *
	Ldx	IIob+Sector
	Lda	Nibl,x
	Sta	Sv4
	Ldy	#0			; No speed check bytes
	Sty	InxPtrH
	Tya				; Flag will tell Sync20 to use data mark fields
	Iny				; Write only one set of self_sync bytes
	Jsr	Sync20			; 6	6	Turn on write circuitry & write self-sync bytes
	Ldy	#0F4			; 2	8
	Lda	#0AD			; 2	10	Last byte of header field
	Bne	Pg1x			; 3	13

Pg1	.Equ *				; Code to write out las 12 bytes of page #1
	Stx	Sv4			; 3
Pg1x	Ldx	Q6L			; 4	17
	Bpl	Pg1x			; 2,3	19/20
	Sta	Q6H			; 4	14	Worst case possible

	Ldx	Page01+2,y		; 4	18
	Lda	Nibl,x			; 4	22
	Sta	Sv3			; 3	25
	Txa				; 2	27
	Lsr	A			; 2	29
	Lsr	A			; 2	31
	Sta	Temp1			; 3	34
	Ldx	Page01+1,y		; 4	38
	Lda	Nibl,x			; 4	42
	Sta	Sv2			; 3	45
	Txa				; 2	47
	And	#0C0			; 2	49
	Ora	Temp1			; 3	52
	Lsr	A			; 2	54
	Ldx	Sv4			; 3	57	61-14 = 47
	Stx	Q6H			; 4	61	Write last byte of previous loop

	Lsr	A			; 2	2
	Sta	Temp1			; 3	5
	Lda	Page01,y			; 4	9
	And	#0C0			; 2	11
	Ora	Temp1			; 3	14
	Lsr	A			; 2	16
	Lsr	A			; 2	18
	Tax				; 2	20
	Lda	Nibl,x			; 4	24
	Sta	Q6H			; 4	28

	Ldx	Page01,y			; 4	4
	Iny				; 2	6
	Iny				; 2	8
	Lda	Nibl,x			; 2	12
$15	Ldx	Q6L			; 4	16
	Bpl	$15			; 2,3	18
	Sta	Q6H			; 4	22

	Lda	Sv2			; 3	3	Second  byte of loop
	Ldx	Sv3			; 3	6	Third byte
	Iny				; 2	8
	Bne	Pg1			; 2,3	10	Fetch rest of 12 bytes
					;		fall thru $|& start on Page #2
;++
;
;--

Pg2	.Equ *				; Code to write out first 255 bytes of Page #2
	Stx	Sv4			; 3
$40	Ldx	Q6L			; 4
	Bpl	$40			; 2,3
	Sta	Q6H			; 4	14	Worst case possible

	Ldx	Page02,y			; 4	18
	Lda	Nibl,x			; 4	22
	Sta	Sv3			; 3	25
	Txa				; 2	27
	Lsr	A			; 2	29
	Lsr	A			; 2	31
	Sta	Temp1			; 3	34
	Ldx	Page02+1,y		; 4	38
	Lda	Nibl,x			; 4	42
	Sta	Sv2			; 3	45
	Txa				; 2	47
	And	#0C0			; 2	49
	Ora	Temp1			; 3	52
	Lsr	A			; 2	54
	Ldx	Sv4			; 3	57	61-14=47
	Stx	Q6H			; 4	61	Write out last byte of previous loop

	Lsr	A			; 2	2
	Sta	Temp1			; 3	5
	Lda	Page02,y			; 4	9
	And	#0C0			; 2	11
	Ora	Temp1			; 3	14
	Lsr	A			; 2	16
	Lsr	A			; 2	18
	Tax				; 2	20
	Lda	Nibl,x			; 4	24
	Sta	Q6H			; 4	28


	Ldx	Page02			; 4	4
	Iny				; 2	6
	Iny				; 2	8
	Lda	Nibl,x			; 4	12
$55	Ldx	Q6L			; 4	16
	Bpl	$55			; 2,3	18
	Sta	Q6H			; 4	22
	Lda	Sv2			; 3	3	Second byte of loop
	Ldx	Sv3			; 3	6	Third byte
	Iny				; 2	8
	Cpy	#Pg2Len			; 2	10
	Bne	Pg2			; 2,3	12	Fetch rest of 255 bytes

	Jsr	WrAX			; 6	26/6	Write Nibls in A and X
	Lda	Page03			; 4	10
	Lda	Nibl,x			; 4	14
	Sta	Sv4			; 3	17
	Lda	CpBy01			; 3	20
	Jsr	WrNibl			; 6	26/6

	Ldy	#02			; 2	8	For use in Pg3
	Ldx	Page02+0FF		; 4	12
	Jsr	WrByteX			; 6	18/6

	Ldx	Page03			; 4	10
	Lda	Nibl,x			; 4	14
	Bne	Pg3x			; 3	17

WrAX	.Equ *				; Write nibls that are in A & X (Sv3)
	Jsr	WrNibl			; 6	32/6
	Lda	Sv3			; 3	9
	Jmp	WrNibl			; 3	12/6

;++
;
;--

WrByte	.Equ *				; Nibbize byte in A-reg before starting
	Tax				; 2
WrByteX	.Equ *				; Use byte in X-reg
	Lda	Nibl,x			; 4

WrNibl	.Equ *				; Wait for handshake bit, then write data in A-reg
	Ldx	Q6L			; 4
	Bpl	WrNibl			; 2,3
	Sta	Q6H			; 4
	Rts				; 6

	.Align	0100
Pg3	.Equ *				; Code to write out first 254 bytes of page #3
	Stx	Sv4			; 3
Pg3x	Ldx	Q6L			; 4
	Bpl	Pg3x			; 2,3
	Sta	Q6H			; 4	14

	Ldx	Page03+2,y		; 4	18
	Lda	Nibl,x			; 4	22
	Sta	Sv3			; 3	25
	Txa				; 2	27
	Lsr	A			; 2	29
	Lsr	A			; 2	31
	Sta	Temp1			; 3	34
	Ldx	Page03			; 4	38
	Lda	Nibl,x			; 4	42
	Sta	Sv2			; 3	45
	Txa				; 2	47
	And	#0C0			; 2	49
	Ora	Temp1			; 3	52
	Lsr	A			; 2	54
	Ldx	Sv4			; 3	57	61-14 = 47
	Stx	Q6H			; 4	61	Write last byte of previous loop

	Lsr	A			; 2	2
	Sta	Temp1			; 3	5
	Lda	Page03			; 4	9
	And	#0C0			; 2	11
	Ora	Temp1			; 3	14
	Lsr	A			; 2	16
	Lsr	A			; 2	18
	Tax				; 2	20
	Lda	Nibl,x			; 4	24
	Sta	Q6H			; 4	28	Composite of 3 bytes

	Ldx	Page03,y			; 4	4
	Iny				; 2	6
	Iny				; 2	8
	Lda	Nibl,x			; 4	12
$85	Ldx	Q6L			; 4	16
	Bpl	$85			; 2,3	18
	Sta	Q6H			; 4	22

	Lda	Sv2			; 3	3	Second byte of loop
	Ldx	Sv3			; 3	6	Third loop
	Iny				; 2	8
	Cpy	#Pg3Len			; 2	10
	Bne	Pg3			; 2,3	12	Fetch rest of 254 bytes

	Jsr	WrAX			; 6	26/6	Write Nibls in A & X (Sv3)
	Ldx	Page03+0FF		; 4	10
	Lda	Nibl,x			; 4	14
	Sta	Sv3			; 3	17
	Lda	CpBy02			; 3	20
	Jsr	WrNibl			; 6	26/6
	Ldx	Page03+0FE		; 4	10
	Lda	Nibl,x			; 4	14
	Jsr	WrAX			; 6	20/6

	Ldy	#Cksum1			; 2	8	Absolute addr of 3 cksum bytes
	Sty	InxPtrL			; 3	11
	Lda	CpCkSum			; 3	14
$95	Ldx	Q6L			; 4	18
	Bpl	$95			; 2,3	20
	Sta	Q6H			; 4	24
	Ldy	#0			; 2	2
$99	Lda	@InxPtrL,y		; 6	8
	Jsr	WrByte			; 3	11/6
	Iny				; 2	8
	Cpy	#3			; 2	10
	Bne	$99			; 2,3	12
					; Fall thru & write final bitslip marks & end
	Lda	DatMk4			; 3
	Jsr	WrNibl			; 6
	Lda	DatMk5			; 3
	Jsr	WrNibl			; 6

ShtOff	.Equ *				; Write 2 bitslip and return /WrUnderRun
	Lda	#0FF			; 2
	Jsr	WrNibl			; 6
	Jsr	WrNibl			; 6
	Clc				; 2
	Lda	Q6L			; 4	Bit6 = UnderRun bit
	And	#40			; 2	Leave only bit 6
	Bne	$38			; 2,3	If = 1 then no underrun occurred
	Lda	#ErrWrt			; Obscure error code #
	Sec				; 2

$38	Sta	Q6H			; 4	Put into write load state
	Ldx	Q7L			; 4	Now into write protect - Sense state
	Rts				; 6

.Page
;--
;		Nibble Table
;
;
; 6-bit to 7-bit nibl conversion table.  codes with more than one pair of
; adjacent zeros or with no adjacent ones (except B7) are excluded.
; Table is now 256 bytes long for use w. any byte.
;--

Nibl	.Equ *

	.Byte	096,097,09A,09B,09D,09E,09F,0A6,0A7,0AB,0AC,0AD
	.Byte	0AE,0AF,0B2,0B3,0B4,0B5,0B6,0B7,0B9,0BA,0BB,0BC
	.Byte	0BD,0BE,0BF,0CB,0CD,0CE,0CF,0D3,0D6,0D7,0D9,0DA
	.Byte	0DB,0DC,0DD,0DE,0DF,0E5,0E6,0E7,0E9,0EA,0EB,0EC
	.Byte	0ED,0EE,0EF,0F2,0F3,0F4,0F5,0F6,0F7,0F9,0FA,0FB
	.Byte	0FC,0FD,0FE,0FF
	.Byte	096,097,09A,09B,09D,09E,09F,0A6,0A7,0AB,0AC,0AD
	.Byte	0AE,0AF,0B2,0B3,0B4,0B5,0B6,0B7,0B9,0BA,0BB,0BC
	.Byte	0BD,0BE,0BF,0CB,0CD,0CE,0CF,0D3,0D6,0D7,0D9,0DA
	.Byte	0DB,0DC,0DD,0DE,0DF,0E5,0E6,0E7,0E9,0EA,0EB,0EC
	.Byte	0ED,0EE,0EF,0F2,0F3,0F4,0F5,0F6,0F7,0F9,0FA,0FB
	.Byte	0FC,0FD,0FE,0FF
	.Byte	096,097,09A,09B,09D,09E,09F,0A6,0A7,0AB,0AC,0AD
	.Byte	0AE,0AF,0B2,0B3,0B4,0B5,0B6,0B7,0B9,0BA,0BB,0BC
	.Byte	0BD,0BE,0BF,0CB,0CD,0CE,0CF,0D3,0D6,0D7,0D9,0DA
	.Byte	0DB,0DC,0DD,0DE,0DF,0E5,0E6,0E7,0E9,0EA,0EB,0EC
	.Byte	0ED,0EE,0EF,0F2,0F3,0F4,0F5,0F6,0F7,0F9,0FA,0FB
	.Byte	0FC,0FD,0FE,0FF
	.Byte	096,097,09A,09B,09D,09E,09F,0A6,0A7,0AB,0AC,0AD
	.Byte	0AE,0AF,0B2,0B3,0B4,0B5,0B6,0B7,0B9,0BA,0BB,0BC
	.Byte	0BD,0BE,0BF,0CB,0CD,0CE,0CF,0D3,0D6,0D7,0D9,0DA
	.Byte	0DB,0DC,0DD,0DE,0DF,0E5,0E6,0E7,0E9,0EA,0EB,0EC
	.Byte	0ED,0EE,0EF,0F2,0F3,0F4,0F5,0F6,0F7,0F9,0FA,0FB
	.Byte	0FC,0FD,0FE,0FF

WideLow	.Equ *			; empirically determined speed tables
	.Byte	003, 023
	.Byte	002, 0E2
	.Byte	002, 09C
	.Byte	002, 057
	.Byte	002, 015
WideH	.Equ *
	.Byte	003, 043
	.Byte	002, 0FE
	.Byte	002, 0B7
	.Byte	002, 070
	.Byte	002, 02B
ThinLow	.Equ *
	.Byte	003, 030
	.Byte	003, 0ED
	.Byte	002, 0A7
	.Byte	002, 062
	.Byte	002, 01E
ThinHih	.Equ *
	.Byte	003, 036
	.Byte	002, 0F3
	.Byte	002, 0AD
	.Byte	002, 066
	.Byte	002, 022

.Page

;++
;
;		Command parsing and testing tables
;
;--

; Command properties and parameters used, one byte per command:
;
; Bits are numbered 0 (LSb) to 7 (MSb)	(1/9/89  ARS)
;
;	Bit		Contents (command requires if set)
;	---		--------
;	0		Drive # & a clamped disk
;	1		Side #
;	2		Sector #
;	3		Track #
;	4		Mask
;	5		Confiramtion byte
;	6		Write protection
;	7		Format/Verify Parameters

TTCDrive	.Equ 001			; Test Table Constant:  Check validity of drive parameter
TTCSide		.Equ 002			; Test Table Constant:  Check validity of side parameter
TTCSectr	.Equ 004			; Test Table Constant:  Check validity of sector parameter
TTCTrack	.Equ 008			; Test Table Constant:  Check validity of track parameter
TTCMask		.Equ 010			; Test Table Constant:  Check validity of mask parameter
TTCFcfm		.Equ 020			; Test Table Constant:  Confirmation byte
TTCWprt		.Equ 040			; Test Table Constant:  Write protection
TTCFvpm		.Equ 080			; Test Table Constant:  Format/Verify

TestTbl	.Byte	TTCDrive+TTCSide+TTCSectr+TTCTrack			; Read
	.Byte	TTCDrive+TTCSide+TTCSectr+TTCTrack+TTCWprt		; Write
	.Byte	TTCDrive						; Unclamp
	.Byte	TTCDrive+TTCSide+TTCTrack+TTCfcfm+TTCWprt+TTCFvpm	; Format
	.Byte	TTCDrive+TTCSide+TTCTrack+TTCFvpm			; Verify
	.Byte	TTCDrive+TTCSide+TTCTrack+TTCFvpm+TTCWprt		; Format track
	.Byte	TTCDrive+TTCSide+TTCTrack				; Verify track
	.Byte	TTCDrive+TTCSide+TTCSectr+TTCTrack			; Read w/o checksum
	.Byte	TTCDrive+TTCSide+TTCSectr+TTCTrack+TTCWprt		; Write w/o checksum
	.Byte	000							; Clamp

TestGoB	.Byte	TTCDrive+TTCSide+TTCTrack				; Seek
	.Byte	000							; Call
	.Byte	000							; ClrSt
	.Byte	TTCMask							; SetIMsk
	.Byte	TTCMask							; ClrIMsk
	.Byte	000							; WaitROM
	.Byte	000							; Drop Dead

.Page
;++
;			Shared ram default tables
;--

ShareRam	.Equ *
	.Byte 0D5			;  0:15		Default Speed Codes For 5 Classes
	.Byte 0C0			; 16:31
	.Byte 0A7			; 32:47
	.Byte 089			; 48:63
	.Byte 064			; 64:79
	.Byte 01E			; ScDly		Speed change delay:  150 ms
	.Byte 004			; HeaDelay	Head settling time:  30 ms - 10 for SpdChk
	.Byte 009			; MaxDdly	DIP sample delay -- used for motor off
RomID	.Byte 088			; ROM identification number (@0018/FCC031)
	.Byte 064			; MaxRetry	Maximum retries count:  100.
	.Byte 002			; MaxRecal	Maximum recallibration count:  1
	.Byte 130.			; StpDly	# 100 usec fro step delay
	.Byte 04F			; MOnDly	Motor on delay:  400 ms - 10 for SpdChk
	ShareSz	.Equ *-ShareRam		; size of shared variable area

;++
;		SecPrTrk == Number of sectors per track
;--

SecPrTRk	.Equ *
	.Byte 12.			;  0:15
	.Byte 11.			; 16:31
	.Byte 10.			; 32:47
	.Byte 9.			; 48:63
	.Byte 8.			; 64:79

;++
;		Two tables -- Address marks & Data marks
;		allows modification by high level software for copy protection
;--

SavAdr	.Equ *
	.Byte 0D5			; First threew bytes indicate start of address field
	.Byte 0AA
	.Byte 096
	.Byte 0DE			; last two bytes finish the address field
	.Byte 0AA

SavDat	.Equ *
	.Byte 0D5			; First three bytes indicate start of data field
	.Byte 0AA
	.Byte 0AD
	.Byte 0DE			; last two bytes finish the data field
	.Byte 0AA

.Page
;++
;
;		WaitRom
;
; WaitRom switches off both motors and then waits until the 68000 diagnostics
; sets location 000 (68K = 000C00) first to #069 and then to #096.  The 6504
; will then do a cold start of the system
;
;--
;
; REGISTERS
;  IN
;	A =	Any value
;	X =	Any value
;	Y =	Any value
;  OUT
;	Returns via a cold start
;
;++

WaitRom	.Equ *				; Entry point for WaitRom
	Jsr	PrkClr0			; Park heads, turn motors off & clear GoByte

; Loop until 69/96 sequence occurrs

WaitRom1	Lda	000			; Wait for #069
	Cmp	#069
	Bne	WaitRom1

WaitRom2	Cmp	000			; Wait for #096
	Beq	WaitRom2

	Sec
	Adc	000			; Will be 0 if = 96
	Bne	Wait
	Rom1
	Jmp	DnWhWt			; Reset the world w/o memory wait

.Page
;++
;
;		Write
;
; Write will write to a Disk/Side/Track/Sector after the sector
; header has been found by RdAddr.  Depending on the command, it
; will perform a checksum operation on the data.  If it is unable to
; read the address header mark after 100. tries it will recalibrate
; and try once more
;
; REGISTER
;  IN
;	All =	Any value
;  OUT
;	All =	Destroyed
;
;--

Write	.Equ *
	Jsr	CreCkSum			; Create a checksum
WriteBF	.Equ *				; Write data using host supplied checksum
	Jsr	PreNib			; Setup data fro reading across page boundaries
	Jsr	Seek
Write3	Jsr	RdAddr			; Find sector
	Bcc	Write16			; Write and if OK return to caller from Write16
	Jsr	BadAddr
	Bcc	Write3
	Lda	#SErrWr			; Write error
	Rts

.Page
;++
;
;	CreCksum -- Create checksum using 524 byte i/o buffer
;
;	Algorithm:
;		A sector is composed of 524 user adata bytes and a 3 byte
;	checksum.  These are translated into 6 bit nibbles which are used to
;	Look up GCR codewords to be written to the disk.  The data is encode
;	as follows:  CSUMA, CSUMB, & CSUMC are "registers" used fo accumulating
;	the checksum.  ByteA, ByteB, & ByteC contain 3 bytes from the data buffer
;
;	1.	Rotate CSUMC left
;		CSUMC[65432107] <- CSUMC[76543210]
;		Carry <- CSUM[7]
;	2.	CSUMA <- CSUMA + ByteA + Carry from step 1
;	3.	ByteA <- ByteA Xor CSUMC
;	4.	CSUMC <- CSUMC + ByteB + Carry from step 2
;	5.	ByteB <- ByteB Xor CSUMA
;	6.	CSUMB <- CSUMB + ByteC + carry from Step 3
;	7.	ByteC <- ByteC Xor CSUC
;
;	Propagation of carry among three checksum bytes:
;
;         ------------------------
;	           v                   v	Note:  Carry out of CsumC is from rotate
;	^--CSUMC <-- CSUMB <-- CSUMA <--
;
; REGISTERS
;  IN
;	All =	Any valye
;  OUT
;	All =	Destroyed
;
;--
.Page

CreCksum	.Equ *				; Entry point for all callers
	Lda	#00
	Sta	Cksum1
	Sta	Cksum2			; Zero only two bytes
	Sta	InxptrL			; Init pointer for 5 cycle index fetch
	Sta	InxptrH
	Inc	InxPtrH			; Start on page 1
	Ldy	#0F4			; Last twelve bytes in page 1

CrTop	.Equ *				; Initially 'A' = 0
	Asl	A			; Move high bit to carry
	Php				; Save status bits on stack
	Adc	#00			; Move carry bit to low bit (8 bit rotate)
	Sta	Cksum3
	Plp				; Restore Status bits
	Lda	@InxPtrL,y		; First of three bytes in loop
	Tax
	Eor	Cksum3			; combine checksum w/ data
	Sta	@InxPtrL,y			; Data ==> buffer
	Txa
	Adc	CkSum1			; Add with above carry
	Sta	Cksum1
	Iny
	Bne	$20			; end of page two data
	Inc	InxPtr			; point to page three

$20	Lda	@InxPtrL,y			; Second of three bytes
	Tax
	Adc	Cksum2			; Add to second checksum byte
	Sta	Cksum2
	Txa
	Eor	Cksum1			; Combine checksum / data
	Sta	@InxPtrL			; Data ==> buffer
	Iny
	Beq	$60			; End of page three data

	Lda	@InxPtrL,y		; Third of three bytes
	Tax				; Save data value
	Eor	Cksum2			; Combine checksum w/ data value
	Sta	@InxPtrL,y		; Data ==> buffer
	Txa				; Restore data value
	Adc	Cksum3			; Add to third checksunm byte leave in A
	Iny
	Bne	CrTop			; Not at page boundary, loop
	Inc	InxPtrH			; start w/ page 2 data
	Bne	CrTop			; branch always taken

$60	Rts				; End of creating a checksum

.Page
;++
;
;				Write Adr Field Subroutine
;
; (16 sector format) writes 27, 40-usec (10-bit) self-sync nibls, adr fields
; 16-sector start marks (0D5,0AA,096), Body (Track, Sector, Side, Volume,
; Checksum), end field marks, and the write turn off nibl.  It then jumps to
; the "WrSync" code which will write the starting sync for the data field,
; write the data fields and then return to the caller.
;--

	.Org	1200
WrSynTrK	.Equ *			; Write a sync track before first track
	Ldy	#00		; 256 sync bytes * 6 to write (about 2 sectors)
	Beq	WrAdr01

WAdr16	.Equ *
	Ldy	FmtGap		;		Default to 6*5 20 usec 'FF's

WrAdr01	Bit	IIob+Track	;		Look for bit six
	Bvc	$23
	Lda	#01
	Ora	IIob+Side
	Sta	IIob+side		;		set bit zero in side

$23	Lda	#1		;		flag for usage of AdrMk 1 & 2
	Jsr	Sync20		; 6	10/10	Write sync fields
	Lda	AdrMk3		; 3	19	Last byte in starting bitslip
	Jsr	WrNibl1		; 6

	Ldy	#02		; 2
$37	Ldx	IIob+Side,y	; 4		Write Track, Sector, then Side
	Jsr	WrByteX		; 6
	Dey
	Bpl	$37

	Ldx	FmtType		; 3	9	Format type
	Jsr	WrByteX		; 6	13/6
	Lda	IIob+Track	; 3	9	Create Address Checksum
	Eor	IIob+Sector	; 3	12
	Eor	IIob+Side		; 3	15
	Eor	FmtType		; 3	18
	Jsr	WrByte		; 6	24/6	Write the address checksum

	Lda	AdrMk4		; 3	9
	Jsr	WrNibl		; 6
	Lda	AdrMk5		; 3	9	Last byte in address field
	Jsr	WrNibl		; 6

	Jsr	ShtOff		; 6	16	Return to Sense mode
	Lda	#ErrHdr		; 2		UnderRun during header
	Bcs	WstTm		; 2,3		Abort upon error
	Jmp	Write16		; 3		Go & write data to disk


WstTm	Rts			; 6	10

.Page
;++
;			RdAdr
;--

RdAdr	.Equ *
	Lda	#0
	Sta	RangeL
	Lda	#RdAdrTmt
	Sta	RangeH
	Jsr	SetRMode		; Setup PAL on Sony to read mode
	Lda	Q6L		; Switch from SENSE to READ

RdAsyn	Inc	RangeL		; 5
	Bne	RdAd1		; 2,3
	Dec	RangeH		; 5
	Beq	RaErr1		; 2,3

RdAd1	Ldx	#00
$24	Lda	Q7L		; 4...
	Bmi	RdAsn1		; 2,3	Valid if high bit = 1
	Dex			; 2
	Bne	$24		; 2,3	Loop 255 times = 85 bytes
	Beq	RaErr1		; 3

RdAsn1	Cmp	AdrMk1		; 2	Address mark 1?
	Bne	RdAsyn		; 2,3	Branch if not

RdAd2	Lda	Q7L		; 4...
	Bpl	RdAd2		; 2,3
	Cmp	AdrMk2		; 2...	Address mark 2?
	Bne	RdAsn1		; 2,3

RdAd3	Lda	Q7L		; 4...
	Bpl	RdAd3		; 2,3
	Cmp	AdrMk3		; 2...
	Bne	RdAsn1		; 2,3

; Marks read now read address
; Carry is set

	Ldx	#AdrsLen		; 2
	Lda	#000		; 2	Clear CSum
Rfld	Sta	CSum		; 3	27
RdAd4	Ldy	Q7L		; 4
	Bpl	RdAd4		; 2	6	Do again if no valid data
	Lda	DNibl,y		; 4	12	Unpack the data
	Sta	CsmFnd,X		; 4	16	Store in FOUND table
	Eor	CSum		; 3	19	Update the checksum
	Dex			; 2	21	Next field
	Bpl	Rfld		; 2,3	24	Loop until "x" become negative
	Tax			; 2		If "CSum" = 0 then AOK
	Bne	RaErr5		; 2,3		No OK, signal on error

; Now compare against two final bytes and make sure at right track and sector

RaSlp1	Lda	Q7L		; 4...
	Bpl	RaSlp1		; 2,3
	Cmp	AdrMk4		; 2...
	Bne	RaErr2		; 2,3
	Lda	#01		; 2
	Bit	SdFnd		; 3
	Beq	RaSlp2		; 2,3
	Lda	#40
	Ora	TrkFnd
	Sta	TrkFnd

RaSlp2	Lda	Q7L		; 4...
	Bpl	RaSlp2		; 2,3
	Cmp	AdrMk5		; 2...
	Bne	RaErr2		; 2,3
	Lda	IIob+Track	; 3
	Cmp	TrkFnd		; 2
	Bne	RaErr4		; 2
	Lda	IIob+Sector	; 3
	Cmp	SecFnd		; 2
	Bne	RaErr3		; 2
	Clc			; 2... No error
	Lda	VolFnd		; Load the disk ID value just read.
	Sta	Iob+DiskID	; Tell host about what type of disk it is
RaExit	Clv			; Clear the overflow bit (previously used for FATAL)
RaExit1	Lda	Q6H		; Switch back from READ to SENSE
	Rts
;  We abort upon seeing first error-no matter what it is.  These all get reset
;  on seeking (even micro stepping).

RaErr1	Inc	RaStrt		; Start bitslip error -- Fatal error
	Sec
	Bcs	RaExit

RaErr2	Inc	RaEnd		; Ending bitslip error
	Sec
	Bcs	RaExit

RaErr5	Inc	RaCSum		; Checksum error
	Sec
	Bcs	RaExit

RaErr4	Inc	RaTrk		; Track error
RaErr6	Sec	
	Bcs	RaExit

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