.Page
;+
;
;			Himem
;		Welcome to Vector City!
; Himem Constants
;
;--

	.Org	02000-00D			; Length of high memory constants
Cpyrt	.Ascii	"C83APPLE"		; This'l show em, we mean business!
RstJmp	.Byte	04C			; A jump vector to the Restart code
	.Word	Restart			; Restart 6504 reset vector
	.Byte	0, 0			; Used to hold checksum for ROM verification

.Page
;++
;			TrackClass will return the class (from 0 to 8) of
;		the track in IIOB+Track in the "Y" register
;
;		returns:		"Y" reg = class of track
;					"A" reg = IIOB+Track
;					"X" reg = unchanged
;--

TrkClss	.Equ *				; Entry point
	Lda	IIOB+Track		; Fetch current track value
	Ldy	#MaxClass		; Maximum class value
$21	Cmp	ClssTbl,Y		; Track >= Table entry?
	Bcs	$42			; Yep
	Dey
	Bne	$21			; Try the next track class
$42	Rts				; "Y" reg = track class value


ClssTbl	.Equ *				; Start of track class table
	.Byte 00			; Track  0:15
	.Byte 10			; Track 16:31
	.Byte 20			; Track 32:47
	.Byte 30			; Track 48:63
	.Byte 40			; Track 64:79

.ABSOLUTE
.PROC LISA
.LIST
.TITLE "Sony DRIVER FOR LISA"
.INCLUDE VAR
.ORG	1000
.INCLUDE TABLES
.INCLUDE TRKCLASS
.INCLUDE FR3TO1
.INCLUDE DENIBBLE
.INCLUDE NEWRWADDR
.INCLUDE Interface
.INCLUDE LOOP
.INCLUDE CLRTRK
.INCLUDE PRENIB
.INCLUDE CMD
.INCLUDE SEEK
.INCLUDE WAITROM
.INCLUDE NMREAD16
.INCLUDE READ
.INCLUDE CRECKSUM
.INCLUDE VFYCKSUM
.INCLUDE WRITE
.INCLUDE WRITE16
.INCLUDE FORMAT
.INCLUDE RECAL
.INCLUDE Npwm
.INCLUDE HIMEM
.End

.PAGE

;---
;				ZERO PAGE MAPPING
;
;	The following equates are for dividing RAM into logical areas;
;	however, as the code grew, this convention was not strictly adhered
;	to and therefore one will find both "LOCAL" and "GLOBAL" variables
;	scattered throughout the RAM area
;+++

IOB	.Equ 00	;  INPUT OUTPUT BLOCK
SHARERAM	.Equ 10	;  READ/WRITE SHARED RAM, INITIALIZED BY 6504 ON BOOT
STATUS	.Equ 20	;  READ ONLY STATUS FROM THE 6504
IIOB	.Equ 30	;  INTERNAL IOB
GLOBALS	.Equ 40	;  6504 INTERNAL GLOBALS
LOCALS	.Equ 68	;  LOCAL VARIABLES

;;	THESE APPEAR, FROM THE LISTING PROVIDED, TO BE HEX NUMBERS UNLESS FOLLOWED BY A DECIMAL
;;	1/6/89 ARS

.PAGE

;---
;
;				IOB
;
;  THE IOB IS ALWAYS COPIED INTO THE INTERNAL IOB (IIOB) AREA BEFORE USAGE
;  SO THAT THE 68K CAN START TO BUILD A NEW COMMAND INTO THE IOB AS SOON AS
;  POSSIBLE.  ALL REFERENMCES TO THE IOB OF IIOB ARE DONE IN THE FOLLOWING
;  FORMAT:
;	IOB	IIOB
;	--------	--------
;  GOBYTE	IOB+GOBYTE	IIOB+GOBYTE
;  DRIVE	IOB+DRIVE	IIOB+DRIVE
;
;+++
IOBSIZE	.Equ 07	;  SIZE OF IOB BLOCK USED FOR PARAMETER PASSING
GOBYTE	.Equ 00	;  COMMAND BYTER FROM 68K

;	00	COMMAND ACCEPTED BY THE 6504, 68K MAY ISSUE A NEW COMMAND
;	80-89	COMMAND FROM 68K TO 6504
;	80	NULL, TESTS HANDSHAKE
;	81	RWTS COMMAND, COMMAND CODE IN 'COMMAND'
;	83	SEEK
;	84	CALL ADDRESS IN 6504
;	85	CLEAR STATUS
;	86	SET MASK
;	87	CLEAR MASK
;	88	WAIT IN ROM
;	89	Go jump to self forever (Their case change ARS)
;
;	01-7f,82,90-ff		*** RESERVED ***

COMMAND	.Equ 01	;  RWTS COMMAND CODE

;	00	READ	Read Read the Data @ Drive/Side/Track/Sector
;	01	WRITE	Write Read the Data @ Drive/Side/Track/Sector
;	02	UNCLAMP	Unclamp the disk in Drive
;	03	FORMAT	Format the disk in Drive
;	04	VERIFY	Verify the disk in Drive
;	05	FORMAT TRACK	Format single Track on the disk in Drive
;	06	VERIFY TRACK	Verify single Track on the disk in Drive
;	07	READBF	Read w/o checksum verification
;	08	WRITEBF	Write w/o checksum creation
;	09	CLAMP	Clamp the disk in Drive
;	0A-FF		*** RESERVED ***

MASK	.Equ COMMAND	;  MASK FOR SETTING AND RESETTING IMSK & IST

;	08	SET OR CLEAR INTERRUPT MASK FOR UPPER DRIVE
;	80	SET OR CLEAR INTERRUPT MASK FOR LOWER DRIVE
;	01	CLEAR DISK INSERTED INTERRUPT FOR UPPER DRIVE
;	10	CLEAR DISK INSERTED INTERRUPT FOR LOWER DRIVE
;	02	CLEAR BUTTOM PRESSED INTERRUPT FOR UPPER DRIVE
;	20	CLEAR BUTTOM PRESSED INTERRUPT FOR LOWER DRIVE
;	04	CLEAR R/W COMMAND COMPLETED INTERRUPT FOR UPPER DRIVE
;	40	CLEAR R/W COMMAND COMPLETED INTERRUPT FOR LOWER DRIVE

ADRL	.Equ COMMAND	;  LOW BYTE OF ADDRESS FOR 6504 CALL
ADRH	.Equ ADRL+1	;  HIGH BYTE OF ADDRESS FOR 6504 CALL
		;  A call to "1FFB" will reset the 65404

DRIVE	.Equ 02	;  DRIVE NUMBER

;	00	DRIVE 0 UPPER DRIVE
;	80	DRIVE 80	LOWER DRIVE

SIDE	.Equ 03	;  SIDE NUMBER

;	00	SIDE 0 UPPER SIDE OF MEDIA
;	01	SIDE 1 LOWER SIDE OF MEDIA

SECTOR	.Equ 04	; SECTOR NUMBER

;	00-15	MAXIMUM DEPENDES ON TRACK NUMBER

TRACK	.Equ 05	;  TRACK NUMBER

;	00-2D	46 TRACKS TOTAL

SPEED	.Equ 06	;  SPEED OVERRIDE

;	00	NOOVERRIDE, SPEED IN DEPENDING ON TRACK NUMBER
;	01-FF	Modifier value added to nominal speed

FMTCNFN	.Equ 07	;  Format configuration byte
		;  Used to ensure format is not executed by mistake
;	FF	FMTCNFM must be = FF for foramt/format track to work

ERRSTAT	.Equ 08	;  ERROR STATUS, RETURNED AFTER R/W COMMANDS
		;  See constants for current error code values

DISKID	.Equ 09	; Current id of the disk last accessed

;	00	UIniFile/DuoFile disk
;	01	Lisa disk
;	02	Macintosh disk

NoSides	.Equ 0A	;  Number of sides of disk drive

DrvError	.Equ 0B	;  Hard errors get returned throught his byte

HostSeek	.Equ 0C	;  When moving the head this location = 'FF'

SekErr	.Equ 0D	;  When seek does not handshake then = '0F'

.Page

;--
;			Shared RAM
;
;  SHARED RAM COMES IN TWO FLAVOERS:  'READ/WRITE' AND 'READ ONLY'.  THE 68K CAN,
;  OF COURSE, READ AND WRITE TO ANY BYTE IN THE RAM AT ANY TIME BUT THIS IS NOT
;  VERY WISE, (ONE MIGHT SAY VERY FOOLISH...), SO THE BY 'READ ONLY' WE MEAN
;  MEMORY THAT NEVER SHOULD BE WRITTEN TO BY THE 68K BUT IS VALID TO READ AT
;  ANY TIME.  TYPICAL 'READ ONY' VARIABLES ARE THE STATUS FLAGS CLMED0 AND
;  CLMPED80 THAT TELLS THE 68K THAT A DISK IS CLAMPED IN DRIVE 0 OR 80
;
;  'READ/WRITE' SHARED MEMORY IS, FOR EXAMPLE, THE IOB BUT IN THIS CASE IT IS
;  A FAMILY OF 'CONSTANTS' SET UP ON COLD START BY THE 6504 TO THEIR DEFAULT
;  VALUES, BUT THEY CAN BE CHANGED AT ANY TIME BY THE 68K TO ANY VALUE.  THERE
;  IS NO CHECKING OF THE RANGE OF THESE VALUES O THE NEW ONE BETTER MAKE SENSE
;  OR THE 6504 MIGHT GO OF TO NEVER, NEVER LAND...
;
;		SHARED:  READ/RWITE
;++

MSpdTbl	.Equ ShareRam
SCDLY	.Equ SHARERAM+5.	;  Speed change delay in 5 ms intervals
HEADELAY	.Equ SHARERAM+6.	;  Head settling time in 5 ms intervals
MAXDDLY	.Equ SHARERAM+7.	;  Timer value in 2/3 second before motor off
ROMIDNUM	.Equ SHARERAM+8.	;  ROM identification number ( 0018/FCC031 )
MAXRETRY	.Equ SHARERAM+9.	;  Maximum number of retries during a read/rwite
MAXRECAL	.Equ SHARERAM+10.	;  Maximum number of recalibrations during a r/w
StpDly	.Equ SHARERAM+11.	;  Step dely time in 100 usec intervals
MONDLY	.Equ SHARERAM+12.	;  Motor on delay time in 5 ms intervals

.Page

;++
;		SHARED:  READ ONLY
;--

Clamped	.Equ Status	;  Disk in Place (=0 EMPYT, =FF CLAMPED)
MtrOn	.Equ Clamped+1	;  DRIVE MOTOR SELECT (0=OFF, FF=ON)

CurTrack	.Equ Status+2	;  value of current track
CurClass	.Equ CurTrack+1	;  Current track class (0:  4)

DrvConn	.Equ Status+4	;  Will be 'FF' if a drive is physically there
FmtType	.Equ DrvConn+1	;  '2' for single, '22' for double sideed

RetryCnt	.Equ Status+6	;  RETRY COUNT
RecalCnt	.Equ RetryCnt+1	;  RECALIBRATION COUNT

ImAlive	.Equ Status+8	; THIS VARIABLE SPINNS AS LONG AS THE MAIN LOOP IS EXECUTING

Counter	.Equ Status+9.	;  GENERAL COUNTER
HoldInx	.Equ Counter+1	;  Holds command index temporarily
FmtGap	.Equ Counter+2	;  Amt * 5 of 20 usec 'FF's to write as selfsync

Imsk	.Equ Status+12.	;  Bits 7 & 3 are mask; if set the drive enabled
DipIntr	.Equ Imsk+1	;  Flag reflects DIP interrupt
OkToGo	.Equ Imsk+2	;  REFLECTS FDIR (=0, FDIRL; <>0, FDIRH)
IST	.Equ Imsk+3	;  INTERRUPT STATUS

;	Bits of IST are numbered for LSb (0) to MSb (7)
;
;	Bit	Meaning
;	---	-------
;	0	Drive 0 disk inserted
;	1	Drive 0 button pressed
;	2	Drive 0 R/W completed
;	3	Logical OR of bit 0,1 & 2
;	4	Drive 80 disk inserted
;	5	Drive 80 button pressed
;	6	Drive 80 R/W completed
;	7	Logical OR of bit 4,5 & 6

AdrMk1	.Equ	IIob+8	;  5 values that indicate start and end of address field
AdrMk2	.Equ	AdrMk1+1
AdrMk3	.Equ	AdrMk1+2
AdrMk4	.Equ	AdrMk1+3
AdrMk5	.Equ	AdrMk1+4

.Page
		; Following 3 byte counter controls both testing
		; for DIP and shutting off teh motors.  When
WtLow	.Equ Globals	; the low 2 bytes = 0 then test for DIP. When
WtMid	.Equ WtLow+1	; the third byte becomes 0 the heads are parked
WtHih	.Equ WTLow+2	; and the motors are turned off
		; For timing and space purposes during writeg
		; of data, an indexed by "y" through zero
INXPTRL	.Equ Globals+3	; pge instruction is used.  The two bytes
INXPTRH	.Equ INXPTRL+1	; hold the base address for the index\.

		; Some constants for timing purposes
K000	.Equ Globals+5	; A constant '00'
K0FF	.Equ K000+1	; A constant 'FF'

		; Following 8 locations hold error counters for
		; various read errors.  The first three are for
		; error w/ reading data and the last five are
		; for errors associated w/ the header.
STSLP	.Equ GLOBALS+8.	; Read Data Starting Bitslip
BSCNT	.Equ StSlp+1	; Read Data ending Bitslip
CSERROR	.Equ StSlp+2	; Read data Checksum error
RASTRT	.Equ StSlp+3	; Read Address Starting Bitslip
RAEND	.Equ StSlp+4	; Read Address Ending Bitslip
RASCTR	.Equ StSlp+5	; Read Address wrong sector
RATRK	.Equ StSlp+6	; Read Address wrong track
RACSUM	.Equ StSlp+7	; Read Address Checksum error
ERRLEN	.Equ 7	; 8 bytes, zero based

CSMFND	.Equ Globals+16.	; CHECKSUM read from disk
VOLFND	.Equ CsmFnd+1		; 0 = UniFile/DuoFile, 1 = Lisa, 2 = Mac
SDFND	.Equ CsmFnd+2		; SIDE FOUND
SECFND	.Equ CsmFnd+3		; SECTOR FOUND
TRKFND	.Equ CsmFnd+4		; TRACK FOUND
CSUM	.Equ CsmFnd+5		; Checksum calculated from ADDRESS data
ADRSLEN	.Equ 4		; LENGTH OF ADDRESS HEADER - 1

TrkFlg	.Equ Globals+22.
MtrFlg	.Equ TrkFlg+1
StpAmt	.Equ TrkFlg+2
Direct	.Equ TrkFlg+3

IndexL	.Equ Globals+26.
IndexH	.Equ IndexL+1
RangeL	.Equ IndexL+2
RangeH	.Equ IndexL+3

CPBY01	.Equ Globals+30.	; Composite byte formed from BUFFER[ 2FF:301 ]
CPBY02	.EQY CPBY01+1		; [ 3FE:3FF ]

CPCKSUM	.Equ Globals+32.	; Composite byte formed from 3 checksum bytes
CKSUM1	.Equ CPCKSUM+1		; First checksum byte
CKSUM2	.Equ CPCKSUM+2		; Second shecksum byte
CKSUM3	.Equ CPCKSUM+3		; Third checksum byte

TCKSM1	.Equ Globals+36.	; During a read of data, the checksum is read
TCKSM2	.Equ TCKSM1+1		; into "CKSM1..3".  A new checksum is created
TCKSM3	.Equ TCKSM1+2		; and stored in these 3 bytes to verify matters

TEMPSEC	.Equ Globals+39.	; TEMPRARY SECTOR COUNTER USED BY FORMAT

.Page

;--
;			LOCAL VARIABLES USED IN ONE OR SEVERAL ROUTINES
;++

RWCSMFLG	.Equ LOCALS		; Flag fro usage of host supplied checksum
DELAY	.Equ LOCALS+1		; COMPUTED DELAY FOR TOTAL SEEK

Sv1	.Equ LOCALS+2		; storage during Write16
Sv2	.Equ Sv1+1
Sv3	.Equ Sv1+2
Sv4	.Equ Sv1+3

TEMP1	.Equ Locals+6.		; 2 Locations for temporary by many routines
TEMP2	.Equ TEMP1+1

DatMk1	.Equ Locals+8		; 5 values that indicate start and end of Data field
DatMk2	.Equ DatMk1+1
DatMk3	.Equ DatMk1+2
DatMk4	.Equ DatMk1+3
DatMk5	.Equ DatMk1+4

LOWCNT	.Equ LOCALS+13.		; Holds value for physiacl interleave count
HIHCNT	.Equ LOWCNT+1.		; Same but opposite/complimentary value
CNTPTR	.Equ LOWCNT+2.		; Pointer to which cnt to use ( high or low )
TOTCNT	.Equ LOWCNT+3.		; Total count of sectors written

TEMP3	.Equ Locals+17.
TEMP4	.Equ TEMP3+1

RtyFlg	.Equ Locals+19.		; flag for use in BadAddr error handling
Uu6	.Equ Locals+20.		; 2 unused locations

Cmdx	.Equ Locals+21.
SaveL	.Equ Locals+22.
SaveH	.Equ Locals+23.
CmdLeng	.Equ 3F		; 64 byte ring buffer of 8 byte IOB's
SavIndex	.Equ 80

; *** NOTE -- Ram from 'C0' to 'FF' is used by the 68K as parameter memory ***

LSTUSED	.Equ 0BF		; last used location in the ZERO PARE RAM

.Page
;--
;
;			CONSTANTS
;
;++

BUFR12SZ	.Equ 0B		; LENGTH OF 12 BYTE BLOCK HEADER - 1
NIBLRETR	.Equ 20		; THE NUMBER OF NIBBLES READ SEARCHING FOR THE
			; FIRST ADDRESS MARK DURING A READ
MAXTRACK	.Equ 4F		; MAXIMUM TRACK NUMBER: 79.
MINTRACK	.Equ 0		; MIMIMUM TRACK NUMBER: 0
MAXCLASS	.Equ 04		; Maximum track class value -- range from 0..4
MINSECNT	.Equ 08		; Minimum sector count
MAXSECNT	.Equ 0C		; Maximum sector count
MINSPEED	.Equ 0D4		; Minimum speed value
MAXSPEED	.Equ 038		; Maximum speed value -- Low # = high speed
OkDly	.Equ 28.

CNFMVAL	.Equ 0FF		; Format configuration check byte
LOW6	.Equ 3F		; mask for low 6 bit

MaxCmd	.Equ 09		; 10 commands return FDirH ( -1 )
CmdNumb	.Equ 07		; Seven commands nao accessed through '81'
NullCmd	.Equ 080		; Null/Handshake command
RwtsCmd	.Equ 091		; Read/Write Track/Sector command value
LwCmdNo	.Equ 083		; Lowest command number ( not including '81' )
ClStsCmd	.Equ 085		; Command to clear interrupt status
WrtCmd	.Equ 01		; Value of command to write data to disk
WrtBfCmd	.Equ 08		; Write data, brute force method
FrmtDsk	.Equ 03		; Value of command host to to format disk
VrfyDsk	.Equ 04		; Value of command host to to verify disk
FrmtTrk	.Equ 05		; Value of command from host to format a track
VrfyTrk	.Equ 06		; Value opf command from host to verify a track

ADM1	.Equ 0D5		; Address mark one
ADM2	.Equ 0AA		; Address mark two
ADM3	.Equ 096		; Address mark three
DDM3	.Equ 0AD		; Data mark three

BitSlp1	.Equ 0DE		; Bit slip mark one
BitSlp2	.Equ 0AA		; Bit slip mark two

RclStep	.Equ 4.		; # of steps to take away from Trk00 during recal
OneScc	.Equ 200.		; constant for a one second wait
TmOutRcl	.Equ 100.		; Timeout for recal wait
RdAdrTmt	.Equ 08.		; Tiomeout for looking for address header
IWMMode	.Equ 01F		; constant to setup IWM modes
TurnRound	.Equ 08.		; 5*8=40 msec turn around time for changing directions

Lrge	.Equ 05.
Smal	.Equ 01.
TblJmp	.Equ 09.
WHih	.Equ 17.		; '11' hex
WLow	.Equ 00.
tLow	.Equ 20.

;  ERROR NUMBERS

GErrCmd	.Equ 01		; Gobyte error:  Invalid command
GErrDrv	.Equ 02		; Gobyte error:  Invalid drive number
GErrSid	.Equ 03		; GoByte error:  Invalid side number
GErrSec	.Equ 04		; Gobyte error:  Invalid Sector number
GErrTrk	.Equ 05		; Gobyte error:  Invalid Track number
GErrMsk	.Equ 06		; Gobyte error:  Invalid mask
GErrClm	.Equ 07		; Gobyte error:  No clamped disk in drive
GErrEna	.Equ 08		; Gobyte error:  Drive not enabled
GErrIntr	.Equ 09		; Gobyte error:  Pending interrupts not cleared
GErrFmPr	.Equ 10.		; Gobyte error:  Invalid format parameter

PErrROM	.Equ 11.		; Program error:  ROM test failed
PErrInt	.Equ 12.		; Program error:  Random IRQ, NMI or BRK

DErrCal	.Equ 13.		; Drive error:  time out while looking for track zero
IWMError	.Equ 14.		; Fatal error:  IWM doesn't respond to commands
StepErr	.Equ 15.		; Handshake diod not occur when stepping
DErrTk0	.Equ 16.		; Drive Error:  Unable to leave track zero location

SErrProt	.Equ 20.		; Errstat error:  Write protect error
SErrFrmt	.Equ 21.		; Errstat error:  Can't verify disk
SErrClmp	.Equ 22.		; Errstat error:  Unable to clamp disk
SErrRd	.Equ 23.		; Errstat error:  Read error
SErrWr	.Equ 24.		; Errstat error:  Write error
SErrUclmp	.Equ 25.		; Errstat error:  Unable to unclamp diskette
SErrNoA9	.Equ 26.		; Errstat error:  Cannot find A9's during chkspd
SErrTmt	.Equ 27.		; Errstat error:  Unable to adjust speed w/in timeout
SErrM1Tk	.Equ 28.		; Errstat error:  Cannot write speed track

ErrHdr	.Equ 30.		; UnderRun while writing header
ErrWrt	.Equ 31.		; UnderRun while writing data fields

.Page
;++
;
;		Data Buffer equates and Bad Block equates
;
;--

StackSt	.Equ 0CF		; Init stack to "01CF" -- push down stack
SctrCnt	.Equ 01D0		; During VERIFY, will no. of bad sectors
TrkNumb	.Equ SctrCnt+1		; Track number where bad sector occurred
SidNumb	.Equ SctrCnt+2		; Side number where bad sector occurred
SctrSav	.Equ SctrCnt+3		; Start of buffer where sector numbers are saved

Page01	.Equ 100		; last 12 bytes of data are for read/write
Bufr12	.Equ 1F4		; last 12 bytes of data for raed/write
Page02	.Equ 200		; 256 bytes of data for read/write
Page03	.Equ 300		;  "

Pg2Len	.Equ 0FF		; # of bytes to read during Wrbf02 loop
Pg3Len	.Equ 0FE		; # of bytes to read during Wrbf03 loop

.Page

;--
;		I/O Space
;++

IOSpace	.Equ 800		; name for beginning of I/O space offsets
Off	.Equ 00		; Offset to switch a phase off
On	.Equ 01		; Offset to switch a phase on
Zero	.Equ 00		; Offset to drive zero
Eighty	.Equ 01		; Offset to drive eighty
Low	.Equ 00		; PwmEna + Low enables output of PWMReg
High	.Equ 01
InWard	.Equ 00		; direction offsets
OutWard	.Equ 01

CA0	.Equ IOSpace		; Control signal 0 for MCI PAL in Sony drive
CA1	.Equ IOSpace+2		; signal 1
CA2	.Equ IOSpace+4		; signal 2
LStrb	.Equ IOSpace+6		; Load strobe -- 0 to 1 to 0 will strobe PAL

MtEna	.Equ IOSpace+8		; Enables output of DrvEna

DrEna	.Equ IOSpace+10.	; = 0 --> drive 0, = 1 ==> drive 80

Q6L	.Equ IOSpace+12.	; Low = Read or Write
Q6H	.Equ Q6L+1		; High = Sense or Write Load
Q7L	.Equ IOSpace+14.	; Low disables writing to disk
Q7H	.Equ Q7L+1		; Enables /WrReq output of IWM

CntEna	.Equ IOSpace+16.	; low enables PWM counter/comparator

PwmEna	.Equ IOSpace+22.	; High enables pulses to Sony, else always low

DisL	.Equ IOSpace+24.	; Memory enable for the 68K
DisH	.Equ DisL+1		; Memory disable for the 68K

Side0Sel	.Equ IOSpace+26.	; Selects side 0
Side1Sel	.Equ Side0Sel+1		; Selects side 1

BootL	.Equ IOSpace+28.	; Disk Diag Line; when High then I'm listening
BootH	.Equ BootL+1

FDirL	.Equ IOSpace+30.	; Deselects the interrupts to the 68K
FDirH	.Equ FDirL+1		; Selects the interrupts to the 68K

PWMReg	.Equ IOSpace+32.	; Selects the PWM register for writing

;

.Page
;++
;			TrackClass will return the class (from 0 to 8) of
;		the track in IIOB+Track in the "Y" register
;
;		returns:		"Y" reg = class of track
;					"A" reg = IIOB+Track
;					"X" reg = unchanged
;--

TrkClss	.Equ *				; Entry point
	Lda	IIOB+Track		; Fetch current track value
	Ldy	#MaxClass		; Maximum class value
$21	Cmp	ClssTbl,Y		; Track >= Table entry?
	Bcs	$42			; Yep
	Dey
	Bne	$21			; Try the next track class
$42	Rts				; "Y" reg = track class value


ClssTbl	.Equ *				; Start of track class table
	.Byte 00			; Track  0:15
	.Byte 10			; Track 16:31
	.Byte 20			; Track 32:47
	.Byte 30			; Track 48:63
	.Byte 40			; Track 64:79

.Page
;++
;--

TimIt	.Equ *
	Lda	#5				; Time 6 pulses
	Sta	Temp2
	Clc					; Should stay clear unless explicitly set
	Jsr	WtZero				; Look for low, then first high
	Bcs	RsOut				; 2,3	10	No edge within timeout period
	Jsr	RsEdge				; 8	8	Now at known locationo
	Bcs	RsOut				; 2,3	10	No edge within timeout period
	Lda	#0				; 2	12
	Sta	RangeL				; 3	15
	Sta	RangeH				; 3	18	Zero both bytes of counter

;++
;	WtZero & RsEdge both have 36 cycles (18.0 uSec) per tick of RangeL:H
;--

$20	Jsr	WtZero				; Look for low
	Bcs	RsOut				; 2,3
	Jsr	RsEdge				; Wait for next edge on pulse
	Bcs	RsOut				; 2,3
	Dec	Temp2				; 5		When less than zero then exit
	Bpl	$20				; 2,3	15*(2+@+%+#) = 180 cycles

RsOut	.Equ *
	Rts					; 6		Common exit point

WtZero	.Equ *
	Bit	K000				; 3		ccV set to Zero
	Bvc	RsEd				; 3	6

RsEdge	.Equ *					;		Look for a rising edge
	Bit	K0FF				; 3	3	ccV eq 0 == low, ccV eq 1 == high
	Bvs	ReEd				; 3	6
RsEd	.Equ *
	Ldy	#00				; 2	8
	Ldx	#0A0				; 2	10	Constant timeout for pulse counting

$10	Dey					; 2	2
	Bne	$20				; 2,3	4,5
	Dex					; 2	6
	Bne	$30				; 2,3	8,9
	Sec					; 2	10	When X-reg = 0 then return error
	Rts

$20	Nop					; 2	7
	Nop					; 2	9	Waste time

$30	Inc	RangeL				; 5	14
	Bne	$40				; 2,3	16,17
	Inc	RangeH				; 5	21
	Bne	$50				; 3	24	Always taken ??

$40	Pha					; 3	20	Waste more time
	Pla					; 4	24

$50	Lda	Q7L				; 4		Bit7=0 ==>tach low, else tach high
	Bvc	$70				; 2,3	30,31	ccV ==> look for low
	Bpl	$90				; 2,3	32,33	If high then fall thru & exit
	Nop					; 2	34
$60	Rts					; 6

$70	Bpl	$60				; 2,3	33,34	If low then exit

$90	Bcc	$10				; 3	36	Always taken?? -- 18.0 uSec loop

ChkLrg	.Equ *
	Lda	#Lrge				; 5
	Sta	Temp1				; For speed adjustment
	Lda	#WLow
	Beq	ChkComm

ChkSml	.Equ *
	Lda	#Smal				; 1
	Sta	Temp1
	Lda	#TLow

;++
;  ChkComm
;     if H < TL
;       then AdjPlus
;     else if H > TL
;       then TstHih
;     else  if L < Tl
;       then AdjPlus
;     else if L = TL
;       then OK
;  TstHih
;     If H > Th
;        then AdjMinus
;     else if H <> Th
;        then OK
;     else if L <= TH
;        then OK
;     else AdjMinus
;--

ChkComm	.Equ *
	Sta	InxPtrL			; Ptr to which constraints ( low of high )
	Lda	CurClass			; Current track class
	Asl	A			; *2 to address word array
	Tay
	Lda	RangeH
	Cmp	@InxPtrL,y		; High must be greater than or equal to lowtable,y
	Bcc	AdjPlus			; High byte low, must spin slower
	Bne	TsHih			; High byte greater -- must see if w/in high boundary
	Inc
	Lda	RangeL
	Cmp	@InxPtrL,y		; Must be greater than or equal to table,y
	Bcc	AdjPlus			; High bytes = and low byte low - slow it down
	Beq	ChkOK			; Both bytes are equal so within range
	Clc
TsHih	.Equ *				; ccC=1 if branched to here so add +1 for not 'Iny'
	Tya
	Adc	#TblJmp			; 9.
	Tay				; Index now points at high side of range
	Lda	@InxPtrL,y
	Cmp	RangeH			; High byte must be <= high boundary
	Bcc	AdjMinus			; High byte is too high, spin disk faster
	Bne	ChkOK			; If <> then low byte must be w/in range
	Iny				; Point @ low byte of boundary value
	Lda	@InxPtrL,y
	Cmp	RangeL			; Low byte is too high, spin disk faster

ChjkOK	.Equ *
	Clc
	Rts

AdjPlus	.Equ *				; ccC = 0 already
	Ldy	CurClass
	Lda	MSpdTbl,y
	Adc	TEmp1			; Add adjustment value
	Sta	MSpdTbl,y
	Sec
	Rts

AdjMinus	.Equ *
	Ldy	CurClass
	Lda	MSpdTbl,y
	Sec
	Sbc	Temp1
	Sta	MSpdTbl,y
	Sec
	Rts

SpdChk	.Equ *				; Main entry point for speed check
	Lda	#WHih			; '11'x
	Sta	InxPtrH
	Jsr	SetTach			; Make sure in Tach sense mode
	Jsr	TimIt			; Time 6 pulses & abort on timeout
	Bcs	SpdErr
	Jsr	ChkLrg			; Must be within +/- 2%
	Bcc	SpdDone
	Lda	#101.			; 100 times total for attempts to adjust
	Sta	Counter

$10	Dec	Counter
	Beq	SpdErr			; Try for 100 times and abort upon inability to adjust
	Jsr	SetSpeed
	Lda	ScDly
	Jsr	Wait
	Jsr	Timit
	Bcs	SpdErr
	Jsr	ChkLrg
	Bcs	$10			; Loop until speed within +/- 2%

$32	Sec				; Make sure error flag is set
	Dec	Counter
	Beq	SpdErr			; Try for 100 times and abort upon inability to adjust
	Jsr	ChkSml			; Now loop until within +/- .5%
	Bcc	SpdDone
	Jsr	SetSpeed
	Lda	ScDelay
	Jsr	Wait
	Jsr	TimIt
	Bcc	$32

SpdErr	.Equ*
	Lda	#SErrTmt

SpdDone	.Equ *
	Rts

.Page
;++
;
;		VfyCksum -- Verify checksum that was just read.
;
; VfyCksum will undo the mess that CreCksum created by xor'ing the
; checksum into the data bytes.  See teh CreCksum description for the
; alogrithm used to understand what is being undone here.
;
; REGISTERS
;  IN
;	All =	Any value
;  OUT
;	All =	Destroyed
;	ccC =	0 if checksum matches
;		1 if checksum does not match
;
; CALLS
;	NONE
;
;--
VfyCksum	.Equ *				; Entry point for all callers
	Lda	#00			; Init temporary checksums to zero
	Sta	TCksm1
	Sta	TCksm2
	Sta	InxPtrl
	Sta	InxPtrH
	Inc	InxPtrH			; Start at page 1
	Ldy	#0F4			; Only last 12 bytes

VfTop	.Equ *
	Asl	A			; Rotate the third checksum byte
	Php				; Save the status bits
	Adc	#00			; Put carry bit into low bit (8 bit rotate)
	Sta	TCksm3			; Save 3rd checksum byte
	Plp				; Restore status bits
	Lda	@InxPtrL,y		; Read 1st byte of 3 byte loop
	Eor	TCksm3			; restore original data
	Sta	@InxPtrL,y
	Adc	TCksm1
	Sta	TCksm1			; And update the checksum
	Iny
	Bne	$20
	Inc	InxPtrH			; Next page

$20	Lda	@InxPtrL,y		; 2nd of 3 byte loop
	Eor	TCksm1			; Restore originl data
	Sta	@InxPtrL,y
	Adc	TCksm2
	Sta	TCksm2			; And update the checksum
	Iny
	Beq	$60			; Last byte to sum

	Lda	@InxPtrL,y		; 3rd byte of 3 byte loop
	Eor	TCksm2			; Restore original data
	Sta	@InxPtrL,y
	Adc	TckSm3			; Update checksum and leave in A
	Iny
	Bne	VfTop			; Not at page boundary, loop
	Inc	InxPtrH			; Next page
	Bne	VfTop			; Branch always taken

$60	Cmp	CkSm2			; 'A' reg has TCksm2
	Bne	$80
	Lda	TCksm3
	Cmp	Cksum3
	Bne	$80
	Lda	TCksm1
	Cmp	Cksum1
	Bne	$80
	Clc
	Rts

$80	Sec
	Rts

.Page
;++
;	Write16
;
; $10	Ldx	Q6L	; 1	1	Assume worst case
;	Bpl	$10	; 3	4	branch taken
;	Ldx	Q6L	; 4	8	bit will be set
;	Bpl	$10	; 2	10	fall thru
;	Sta	Q6H	; 4	14	put the data into reg
; 31 cycles max after bit is set before UnderRun bit is set.  Using above code
; as start of time critical code,
; total time = ((32-14)+31) = 49 cycles
;--
.Page
	.Org	1A00
Write16	.Equ *
	Ldx	IIob+Sector
	Lda	Nibl,x
	Sta	Sv4
	Ldy	#0			; No speed check bytes
	Sty	InxPtrH
	Tya				; Flag will tell Sync20 to use data mark fields
	Iny				; Write only one set of self_sync bytes
	Jsr	Sync20			; 6	6	Turn on write circuitry & write self-sync bytes
	Ldy	#0F4			; 2	8
	Lda	#0AD			; 2	10	Last byte of header field
	Bne	Pg1x			; 3	13

Pg1	.Equ *				; Code to write out las 12 bytes of page #1
	Stx	Sv4			; 3
Pg1x	Ldx	Q6L			; 4	17
	Bpl	Pg1x			; 2,3	19/20
	Sta	Q6H			; 4	14	Worst case possible

	Ldx	Page01+2,y		; 4	18
	Lda	Nibl,x			; 4	22
	Sta	Sv3			; 3	25
	Txa				; 2	27
	Lsr	A			; 2	29
	Lsr	A			; 2	31
	Sta	Temp1			; 3	34
	Ldx	Page01+1,y		; 4	38
	Lda	Nibl,x			; 4	42
	Sta	Sv2			; 3	45
	Txa				; 2	47
	And	#0C0			; 2	49
	Ora	Temp1			; 3	52
	Lsr	A			; 2	54
	Ldx	Sv4			; 3	57	61-14 = 47
	Stx	Q6H			; 4	61	Write last byte of previous loop

	Lsr	A			; 2	2
	Sta	Temp1			; 3	5
	Lda	Page01,y			; 4	9
	And	#0C0			; 2	11
	Ora	Temp1			; 3	14
	Lsr	A			; 2	16
	Lsr	A			; 2	18
	Tax				; 2	20
	Lda	Nibl,x			; 4	24
	Sta	Q6H			; 4	28

	Ldx	Page01,y			; 4	4
	Iny				; 2	6
	Iny				; 2	8
	Lda	Nibl,x			; 2	12
$15	Ldx	Q6L			; 4	16
	Bpl	$15			; 2,3	18
	Sta	Q6H			; 4	22

	Lda	Sv2			; 3	3	Second  byte of loop
	Ldx	Sv3			; 3	6	Third byte
	Iny				; 2	8
	Bne	Pg1			; 2,3	10	Fetch rest of 12 bytes
					;		fall thru $|& start on Page #2
;++
;
;--

Pg2	.Equ *				; Code to write out first 255 bytes of Page #2
	Stx	Sv4			; 3
$40	Ldx	Q6L			; 4
	Bpl	$40			; 2,3
	Sta	Q6H			; 4	14	Worst case possible

	Ldx	Page02,y			; 4	18
	Lda	Nibl,x			; 4	22
	Sta	Sv3			; 3	25
	Txa				; 2	27
	Lsr	A			; 2	29
	Lsr	A			; 2	31
	Sta	Temp1			; 3	34
	Ldx	Page02+1,y		; 4	38
	Lda	Nibl,x			; 4	42
	Sta	Sv2			; 3	45
	Txa				; 2	47
	And	#0C0			; 2	49
	Ora	Temp1			; 3	52
	Lsr	A			; 2	54
	Ldx	Sv4			; 3	57	61-14=47
	Stx	Q6H			; 4	61	Write out last byte of previous loop

	Lsr	A			; 2	2
	Sta	Temp1			; 3	5
	Lda	Page02,y			; 4	9
	And	#0C0			; 2	11
	Ora	Temp1			; 3	14
	Lsr	A			; 2	16
	Lsr	A			; 2	18
	Tax				; 2	20
	Lda	Nibl,x			; 4	24
	Sta	Q6H			; 4	28


	Ldx	Page02			; 4	4
	Iny				; 2	6
	Iny				; 2	8
	Lda	Nibl,x			; 4	12
$55	Ldx	Q6L			; 4	16
	Bpl	$55			; 2,3	18
	Sta	Q6H			; 4	22
	Lda	Sv2			; 3	3	Second byte of loop
	Ldx	Sv3			; 3	6	Third byte
	Iny				; 2	8
	Cpy	#Pg2Len			; 2	10
	Bne	Pg2			; 2,3	12	Fetch rest of 255 bytes

	Jsr	WrAX			; 6	26/6	Write Nibls in A and X
	Lda	Page03			; 4	10
	Lda	Nibl,x			; 4	14
	Sta	Sv4			; 3	17
	Lda	CpBy01			; 3	20
	Jsr	WrNibl			; 6	26/6

	Ldy	#02			; 2	8	For use in Pg3
	Ldx	Page02+0FF		; 4	12
	Jsr	WrByteX			; 6	18/6

	Ldx	Page03			; 4	10
	Lda	Nibl,x			; 4	14
	Bne	Pg3x			; 3	17

WrAX	.Equ *				; Write nibls that are in A & X (Sv3)
	Jsr	WrNibl			; 6	32/6
	Lda	Sv3			; 3	9
	Jmp	WrNibl			; 3	12/6

;++
;
;--

WrByte	.Equ *				; Nibbize byte in A-reg before starting
	Tax				; 2
WrByteX	.Equ *				; Use byte in X-reg
	Lda	Nibl,x			; 4

WrNibl	.Equ *				; Wait for handshake bit, then write data in A-reg
	Ldx	Q6L			; 4
	Bpl	WrNibl			; 2,3
	Sta	Q6H			; 4
	Rts				; 6

	.Align	0100
Pg3	.Equ *				; Code to write out first 254 bytes of page #3
	Stx	Sv4			; 3
Pg3x	Ldx	Q6L			; 4
	Bpl	Pg3x			; 2,3
	Sta	Q6H			; 4	14

	Ldx	Page03+2,y		; 4	18
	Lda	Nibl,x			; 4	22
	Sta	Sv3			; 3	25
	Txa				; 2	27
	Lsr	A			; 2	29
	Lsr	A			; 2	31
	Sta	Temp1			; 3	34
	Ldx	Page03			; 4	38
	Lda	Nibl,x			; 4	42
	Sta	Sv2			; 3	45
	Txa				; 2	47
	And	#0C0			; 2	49
	Ora	Temp1			; 3	52
	Lsr	A			; 2	54
	Ldx	Sv4			; 3	57	61-14 = 47
	Stx	Q6H			; 4	61	Write last byte of previous loop

	Lsr	A			; 2	2
	Sta	Temp1			; 3	5
	Lda	Page03			; 4	9
	And	#0C0			; 2	11
	Ora	Temp1			; 3	14
	Lsr	A			; 2	16
	Lsr	A			; 2	18
	Tax				; 2	20
	Lda	Nibl,x			; 4	24
	Sta	Q6H			; 4	28	Composite of 3 bytes

	Ldx	Page03,y			; 4	4
	Iny				; 2	6
	Iny				; 2	8
	Lda	Nibl,x			; 4	12
$85	Ldx	Q6L			; 4	16
	Bpl	$85			; 2,3	18
	Sta	Q6H			; 4	22

	Lda	Sv2			; 3	3	Second byte of loop
	Ldx	Sv3			; 3	6	Third loop
	Iny				; 2	8
	Cpy	#Pg3Len			; 2	10
	Bne	Pg3			; 2,3	12	Fetch rest of 254 bytes

	Jsr	WrAX			; 6	26/6	Write Nibls in A & X (Sv3)
	Ldx	Page03+0FF		; 4	10
	Lda	Nibl,x			; 4	14
	Sta	Sv3			; 3	17
	Lda	CpBy02			; 3	20
	Jsr	WrNibl			; 6	26/6
	Ldx	Page03+0FE		; 4	10
	Lda	Nibl,x			; 4	14
	Jsr	WrAX			; 6	20/6

	Ldy	#Cksum1			; 2	8	Absolute addr of 3 cksum bytes
	Sty	InxPtrL			; 3	11
	Lda	CpCkSum			; 3	14
$95	Ldx	Q6L			; 4	18
	Bpl	$95			; 2,3	20
	Sta	Q6H			; 4	24
	Ldy	#0			; 2	2
$99	Lda	@InxPtrL,y		; 6	8
	Jsr	WrByte			; 3	11/6
	Iny				; 2	8
	Cpy	#3			; 2	10
	Bne	$99			; 2,3	12
					; Fall thru & write final bitslip marks & end
	Lda	DatMk4			; 3
	Jsr	WrNibl			; 6
	Lda	DatMk5			; 3
	Jsr	WrNibl			; 6

ShtOff	.Equ *				; Write 2 bitslip and return /WrUnderRun
	Lda	#0FF			; 2
	Jsr	WrNibl			; 6
	Jsr	WrNibl			; 6
	Clc				; 2
	Lda	Q6L			; 4	Bit6 = UnderRun bit
	And	#40			; 2	Leave only bit 6
	Bne	$38			; 2,3	If = 1 then no underrun occurred
	Lda	#ErrWrt			; Obscure error code #
	Sec				; 2

$38	Sta	Q6H			; 4	Put into write load state
	Ldx	Q7L			; 4	Now into write protect - Sense state
	Rts				; 6

.Page
;--
;		Nibble Table
;
;
; 6-bit to 7-bit nibl conversion table.  codes with more than one pair of
; adjacent zeros or with no adjacent ones (except B7) are excluded.
; Table is now 256 bytes long for use w. any byte.
;--

Nibl	.Equ *

	.Byte	096,097,09A,09B,09D,09E,09F,0A6,0A7,0AB,0AC,0AD
	.Byte	0AE,0AF,0B2,0B3,0B4,0B5,0B6,0B7,0B9,0BA,0BB,0BC
	.Byte	0BD,0BE,0BF,0CB,0CD,0CE,0CF,0D3,0D6,0D7,0D9,0DA
	.Byte	0DB,0DC,0DD,0DE,0DF,0E5,0E6,0E7,0E9,0EA,0EB,0EC
	.Byte	0ED,0EE,0EF,0F2,0F3,0F4,0F5,0F6,0F7,0F9,0FA,0FB
	.Byte	0FC,0FD,0FE,0FF
	.Byte	096,097,09A,09B,09D,09E,09F,0A6,0A7,0AB,0AC,0AD
	.Byte	0AE,0AF,0B2,0B3,0B4,0B5,0B6,0B7,0B9,0BA,0BB,0BC
	.Byte	0BD,0BE,0BF,0CB,0CD,0CE,0CF,0D3,0D6,0D7,0D9,0DA
	.Byte	0DB,0DC,0DD,0DE,0DF,0E5,0E6,0E7,0E9,0EA,0EB,0EC
	.Byte	0ED,0EE,0EF,0F2,0F3,0F4,0F5,0F6,0F7,0F9,0FA,0FB
	.Byte	0FC,0FD,0FE,0FF
	.Byte	096,097,09A,09B,09D,09E,09F,0A6,0A7,0AB,0AC,0AD
	.Byte	0AE,0AF,0B2,0B3,0B4,0B5,0B6,0B7,0B9,0BA,0BB,0BC
	.Byte	0BD,0BE,0BF,0CB,0CD,0CE,0CF,0D3,0D6,0D7,0D9,0DA
	.Byte	0DB,0DC,0DD,0DE,0DF,0E5,0E6,0E7,0E9,0EA,0EB,0EC
	.Byte	0ED,0EE,0EF,0F2,0F3,0F4,0F5,0F6,0F7,0F9,0FA,0FB
	.Byte	0FC,0FD,0FE,0FF
	.Byte	096,097,09A,09B,09D,09E,09F,0A6,0A7,0AB,0AC,0AD
	.Byte	0AE,0AF,0B2,0B3,0B4,0B5,0B6,0B7,0B9,0BA,0BB,0BC
	.Byte	0BD,0BE,0BF,0CB,0CD,0CE,0CF,0D3,0D6,0D7,0D9,0DA
	.Byte	0DB,0DC,0DD,0DE,0DF,0E5,0E6,0E7,0E9,0EA,0EB,0EC
	.Byte	0ED,0EE,0EF,0F2,0F3,0F4,0F5,0F6,0F7,0F9,0FA,0FB
	.Byte	0FC,0FD,0FE,0FF

WideLow	.Equ *			; empirically determined speed tables
	.Byte	003, 023
	.Byte	002, 0E2
	.Byte	002, 09C
	.Byte	002, 057
	.Byte	002, 015
WideH	.Equ *
	.Byte	003, 043
	.Byte	002, 0FE
	.Byte	002, 0B7
	.Byte	002, 070
	.Byte	002, 02B
ThinLow	.Equ *
	.Byte	003, 030
	.Byte	003, 0ED
	.Byte	002, 0A7
	.Byte	002, 062
	.Byte	002, 01E
ThinHih	.Equ *
	.Byte	003, 036
	.Byte	002, 0F3
	.Byte	002, 0AD
	.Byte	002, 066
	.Byte	002, 022

.Page

;++
;
;		Command parsing and testing tables
;
;--

; Command properties and parameters used, one byte per command:
;
; Bits are numbered 0 (LSb) to 7 (MSb)	(1/9/89  ARS)
;
;	Bit		Contents (command requires if set)
;	---		--------
;	0		Drive # & a clamped disk
;	1		Side #
;	2		Sector #
;	3		Track #
;	4		Mask
;	5		Confiramtion byte
;	6		Write protection
;	7		Format/Verify Parameters

TTCDrive	.Equ 001			; Test Table Constant:  Check validity of drive parameter
TTCSide		.Equ 002			; Test Table Constant:  Check validity of side parameter
TTCSectr	.Equ 004			; Test Table Constant:  Check validity of sector parameter
TTCTrack	.Equ 008			; Test Table Constant:  Check validity of track parameter
TTCMask		.Equ 010			; Test Table Constant:  Check validity of mask parameter
TTCFcfm		.Equ 020			; Test Table Constant:  Confirmation byte
TTCWprt		.Equ 040			; Test Table Constant:  Write protection
TTCFvpm		.Equ 080			; Test Table Constant:  Format/Verify

TestTbl	.Byte	TTCDrive+TTCSide+TTCSectr+TTCTrack			; Read
	.Byte	TTCDrive+TTCSide+TTCSectr+TTCTrack+TTCWprt		; Write
	.Byte	TTCDrive						; Unclamp
	.Byte	TTCDrive+TTCSide+TTCTrack+TTCfcfm+TTCWprt+TTCFvpm	; Format
	.Byte	TTCDrive+TTCSide+TTCTrack+TTCFvpm			; Verify
	.Byte	TTCDrive+TTCSide+TTCTrack+TTCFvpm+TTCWprt		; Format track
	.Byte	TTCDrive+TTCSide+TTCTrack				; Verify track
	.Byte	TTCDrive+TTCSide+TTCSectr+TTCTrack			; Read w/o checksum
	.Byte	TTCDrive+TTCSide+TTCSectr+TTCTrack+TTCWprt		; Write w/o checksum
	.Byte	000							; Clamp

TestGoB	.Byte	TTCDrive+TTCSide+TTCTrack				; Seek
	.Byte	000							; Call
	.Byte	000							; ClrSt
	.Byte	TTCMask							; SetIMsk
	.Byte	TTCMask							; ClrIMsk
	.Byte	000							; WaitROM
	.Byte	000							; Drop Dead

.Page
;++
;			Shared ram default tables
;--

ShareRam	.Equ *
	.Byte 0D5			;  0:15		Default Speed Codes For 5 Classes
	.Byte 0C0			; 16:31
	.Byte 0A7			; 32:47
	.Byte 089			; 48:63
	.Byte 064			; 64:79
	.Byte 01E			; ScDly		Speed change delay:  150 ms
	.Byte 004			; HeaDelay	Head settling time:  30 ms - 10 for SpdChk
	.Byte 009			; MaxDdly	DIP sample delay -- used for motor off
RomID	.Byte 088			; ROM identification number (@0018/FCC031)
	.Byte 064			; MaxRetry	Maximum retries count:  100.
	.Byte 002			; MaxRecal	Maximum recallibration count:  1
	.Byte 130.			; StpDly	# 100 usec fro step delay
	.Byte 04F			; MOnDly	Motor on delay:  400 ms - 10 for SpdChk
	ShareSz	.Equ *-ShareRam		; size of shared variable area

;++
;		SecPrTrk == Number of sectors per track
;--

SecPrTRk	.Equ *
	.Byte 12.			;  0:15
	.Byte 11.			; 16:31
	.Byte 10.			; 32:47
	.Byte 9.			; 48:63
	.Byte 8.			; 64:79

;++
;		Two tables -- Address marks & Data marks
;		allows modification by high level software for copy protection
;--

SavAdr	.Equ *
	.Byte 0D5			; First threew bytes indicate start of address field
	.Byte 0AA
	.Byte 096
	.Byte 0DE			; last two bytes finish the address field
	.Byte 0AA

SavDat	.Equ *
	.Byte 0D5			; First three bytes indicate start of data field
	.Byte 0AA
	.Byte 0AD
	.Byte 0DE			; last two bytes finish the data field
	.Byte 0AA

.Page
;++
;
;		WaitRom
;
; WaitRom switches off both motors and then waits until the 68000 diagnostics
; sets location 000 (68K = 000C00) first to #069 and then to #096.  The 6504
; will then do a cold start of the system
;
;--
;
; REGISTERS
;  IN
;	A =	Any value
;	X =	Any value
;	Y =	Any value
;  OUT
;	Returns via a cold start
;
;++

WaitRom	.Equ *				; Entry point for WaitRom
	Jsr	PrkClr0			; Park heads, turn motors off & clear GoByte

; Loop until 69/96 sequence occurrs

WaitRom1	Lda	000			; Wait for #069
	Cmp	#069
	Bne	WaitRom1

WaitRom2	Cmp	000			; Wait for #096
	Beq	WaitRom2

	Sec
	Adc	000			; Will be 0 if = 96
	Bne	Wait
	Rom1
	Jmp	DnWhWt			; Reset the world w/o memory wait