Thread
Memory Addressing Questions
I've been looking into the memory subsystem of the IIsi and I noticed a glaring difference between the address lines between Bank A on the MoBo and the SIMM Slots of Bank B:
The MDU (Memory Decoding Unit) Controller ASIC sends 12 bits of addressing shared by the SIMMs in bank B, but only 8 bits for the DRAM ICs in Bank A.
My guess is that this is due to the organization of the individual DRAM ICs, their limited capacities and number of address lines. I'm hoping that the way the control signals organize and the addressing of the four pairs of DRAMs translates into addressing four 16MB SIMMs in Bank A . . .
. . . but my concern is that this might be a basic limitation on expansion of Bank A that's built into the MDU.
Comments. please?
The MDU (Memory Decoding Unit) Controller ASIC sends 12 bits of addressing shared by the SIMMs in bank B, but only 8 bits for the DRAM ICs in Bank A.
My guess is that this is due to the organization of the individual DRAM ICs, their limited capacities and number of address lines. I'm hoping that the way the control signals organize and the addressing of the four pairs of DRAMs translates into addressing four 16MB SIMMs in Bank A . . .
. . . but my concern is that this might be a basic limitation on expansion of Bank A that's built into the MDU.
Comments. please?
8 bits is all that's needed to address the fixed 1 MB of memory in bank A, arranged as it is using 256k x 4 chips.
2^(8 row addresses + 8 column addresses + 4 bits) * 8 chips == 8 megabits == 1 megabyte.
Why bother routing more lines that are just going to force you to allocate more gates for buffers and multiplexers, add to the capacitive load, and take up valuable PCB space, while serving no useful purpose whatsoever?
2^(8 row addresses + 8 column addresses + 4 bits) * 8 chips == 8 megabits == 1 megabyte.
Why bother routing more lines that are just going to force you to allocate more gates for buffers and multiplexers, add to the capacitive load, and take up valuable PCB space, while serving no useful purpose whatsoever?
I know it can address 4MB of RAM in Bank A, uni did that upgrade.
I'm looking into adapting four, double banked 32MB 72-pin SIMMs to the SIMM slots in Bank B. One bank of each to be addressed normally as Bank B, filled with four 16MB SIMMs and the other Bank addressed as Bank A and stuffed with the same. Mobo DRAM and Video Cnnector to be removed, so there's no attempted buffering of DRAM as Vampire VRAM.
It's a stupid Mac trick, why else would I be trying to do it? :lol:
I'm looking into adapting four, double banked 32MB 72-pin SIMMs to the SIMM slots in Bank B. One bank of each to be addressed normally as Bank B, filled with four 16MB SIMMs and the other Bank addressed as Bank A and stuffed with the same. Mobo DRAM and Video Cnnector to be removed, so there's no attempted buffering of DRAM as Vampire VRAM.
It's a stupid Mac trick, why else would I be trying to do it? :lol:
I am wondering if this 16 megs of ram AI is sending me is going to work… in the IIsi
8 chips
2megs per chip.
8 chips
2megs per chip.
also:
i just ran 7.5.5 on my mac II
its only got 4 megs of ram installed. just like the onboard ram of the IIsi.
for some odd reason it would only allow me up to 12 megs of Virtual memory.
where it seemed like the IIsi would let me make the paging file as big as i wanted. 50mb +
The hard drive that is in the mac II is a 700mb quantum, not a 73 gig hd like what i have in the IIsi.
the boot partition in the IIsi was still only 1.7 gb.
I am aware the MacII is only a 68020.
i just ran 7.5.5 on my mac II
its only got 4 megs of ram installed. just like the onboard ram of the IIsi.
for some odd reason it would only allow me up to 12 megs of Virtual memory.
where it seemed like the IIsi would let me make the paging file as big as i wanted. 50mb +
The hard drive that is in the mac II is a 700mb quantum, not a 73 gig hd like what i have in the IIsi.
the boot partition in the IIsi was still only 1.7 gb.
I am aware the MacII is only a 68020.
Ya, you need a card. The FPU I think? I don't recall, its been so long since I played with a IIsi. But pretty sure it needs an FPU or something to be able to set it higher. Then again, I could be wrong!
lol i just remembered that its dirty and needs mode32 anyways.
or does it? i should install mode32 and see what happens.
too bad its on a 1.44 disk… humm. floppy emu to the rescue.
or does it? i should install mode32 and see what happens.
too bad its on a 1.44 disk… humm. floppy emu to the rescue.
Hmmm... maybe that is what you need. I can't recall! All I remember is that I did not have much love for the IIsi, the two we had in the lab among a few Iici and many 6100/66!
I installed mode32 and toggled 32bit mode. rebooted and then i was able to select as much VM as I wanted, With the Mac II.
Ah! Good to know. Now I will forget into another 10 years.
You need 9 address bits to get 4 MB in bank A. It's either already there, or uni put it there.
Four "double-banked" 72-pin SIMMs somehow wired as two banks per SIMM makes 8 banks. Don't forget a bank of 30-pin SIMMs is 4 modules because each is 8 bits wide, and you need 4 together to get the 32 bits that will fill the data bus. One 72-pin SIMM is already 32 bits wide.
Four "double-banked" 72-pin SIMMs somehow wired as two banks per SIMM makes 8 banks. Don't forget a bank of 30-pin SIMMs is 4 modules because each is 8 bits wide, and you need 4 together to get the 32 bits that will fill the data bus. One 72-pin SIMM is already 32 bits wide.
Yep, using the control lines I can access just the necessary sections of each 72-pin SIMM needed to output the 8bits of needed to make the 32bit word in each access far Banks A & B . . .
. . . figuring out how the Data and Addressing is multiplexed(?) in the four 74ALS275 3-State Bus Transceivers should be a big help . . .
. . . or a major hindrance! ;D
It looks like I need to reflect the Control, Data and Address lines of Bank A back onto the bus for Bank B and find or synthesize a Bank Select in order to make this work. I'm hoping I can manage to do that on the two n.c. pins of the 30-pin SIMMs/Slots, dunno, we'll see. Worst case scenario for that appears to be the need to put a circuit on a PCB somewhere between MDU and Bank A to make a gate circuit on my 30-pin to 72-pin adapters work as planned.
Gotta love playing with a 20-33MHz memory bus! :
This thread was a false alarm, I forgot about the SE/30 and IIci using MDU for full A & B SIMM bankage. All the lines are there, with just resistor packs between them and the Bank B SIMMs/Bank A DRAM ICs.
The killer is that I don't really have any need to do this hack, the Rocket, its onboard memory banks and its Fast SCSI II storage subsystem will be the main CPU and I/O in the SuperIIsi under RocketShare. This hack is really just for fun!
. . . figuring out how the Data and Addressing is multiplexed(?) in the four 74ALS275 3-State Bus Transceivers should be a big help . . .
. . . or a major hindrance! ;D
It looks like I need to reflect the Control, Data and Address lines of Bank A back onto the bus for Bank B and find or synthesize a Bank Select in order to make this work. I'm hoping I can manage to do that on the two n.c. pins of the 30-pin SIMMs/Slots, dunno, we'll see. Worst case scenario for that appears to be the need to put a circuit on a PCB somewhere between MDU and Bank A to make a gate circuit on my 30-pin to 72-pin adapters work as planned.
Gotta love playing with a 20-33MHz memory bus! :
This thread was a false alarm, I forgot about the SE/30 and IIci using MDU for full A & B SIMM bankage. All the lines are there, with just resistor packs between them and the Bank B SIMMs/Bank A DRAM ICs.
The killer is that I don't really have any need to do this hack, the Rocket, its onboard memory banks and its Fast SCSI II storage subsystem will be the main CPU and I/O in the SuperIIsi under RocketShare. This hack is really just for fun!
its already there… i didn't do anything other then change the chips.
i am hoping there is going to be enough to address these 2m chips to give me 16 megs onboard!\
well on here with the IIsi and AI's Q605 as well!
i am hoping there is going to be enough to address these 2m chips to give me 16 megs onboard!\
well on here with the IIsi and AI's Q605 as well!
Do your higher capacity DRAMs have the same pinout as the stock ICs?
Yes they do. the new 2m chips have the same pinout as the oem chips. MinerAI found them.
It would be really awesome if they work…
but to be honest, If they don't work for what ever reasons. (in the IIsi)
Hey, i'm happy with 4mb's in the IIsi, at-least that works.
It would be really awesome if they work…
but to be honest, If they don't work for what ever reasons. (in the IIsi)
Hey, i'm happy with 4mb's in the IIsi, at-least that works.
Yeah, and since that's the minimum for a small System 7.1.x install, that's pretty spiffy.
And it's four more megabytes more for the total (built-in plus a full bank of SIMMs).
c
A couple of patch wires and resistors might just do the trick if it doesn't work out o inside the box. [}] ]'>
] ]'>
It's late, I'm tired and visions of Block Diagrams and Schematics are dancing around in my head. |)
I checked out the 74ALS245 function and it looks to be the video buffering mechanism. I neglected to mention that the 8 address bits were not a subset of the address bits heading to the Simms in Bank B. They originate from entirely different pins on MDU. I'm guessing the IIci and IIsi use those eight separate address bits for the buffered DRAM as Vampire VRAM setup in both machines.
If there's a Video Card in the IIsi running the monitor and nothing hooked up to the DA-19 connector on the MoBo at startup, then Bank A is never buffered by the 245s from the main memory bus. Bank A would appear to be contiguous with Bank B and its twelve dedicated addressing lines running from different pins on MDU in Bank A's unbuffered state.
Looks to me like you might have a shot at getting al's 16MB of DRAM ICs to work in Bank A if you aren't using that dratted Vampire Video kluge, uni.
Then again . . . :
I checked out the 74ALS245 function and it looks to be the video buffering mechanism. I neglected to mention that the 8 address bits were not a subset of the address bits heading to the Simms in Bank B. They originate from entirely different pins on MDU. I'm guessing the IIci and IIsi use those eight separate address bits for the buffered DRAM as Vampire VRAM setup in both machines.
If there's a Video Card in the IIsi running the monitor and nothing hooked up to the DA-19 connector on the MoBo at startup, then Bank A is never buffered by the 245s from the main memory bus. Bank A would appear to be contiguous with Bank B and its twelve dedicated addressing lines running from different pins on MDU in Bank A's unbuffered state.
Looks to me like you might have a shot at getting al's 16MB of DRAM ICs to work in Bank A if you aren't using that dratted Vampire Video kluge, uni.
Then again . . . :
Head-desk-head-desk-head-desk . . . :I
OOPSIE!!!! When I was up late last night I misread the schematic for the IIsi and never actually counted the lines.
I just put red lines emanating from the proper legs of the MDU in my AI file, counted them to cross-check . . . and came up with too many!
TEN address lines and the W/E line were what I counted for a total of eleven. Took a gmuch closer look at the schematic again and realized it said "A0-A9" NOT "A0-A7" so much of my concern just vanished.
You may have enough address lines for al's bigchips to work in Bank A of the IIsi, uni!
OOPSIE!!!! When I was up late last night I misread the schematic for the IIsi and never actually counted the lines.
I just put red lines emanating from the proper legs of the MDU in my AI file, counted them to cross-check . . . and came up with too many!
TEN address lines and the W/E line were what I counted for a total of eleven. Took a gmuch closer look at the schematic again and realized it said "A0-A9" NOT "A0-A7" so much of my concern just vanished.
You may have enough address lines for al's bigchips to work in Bank A of the IIsi, uni!
10 address lines are needed for 4 Mbit x 4 DRAMs, so I'd say you're good to go. (If you're making 16 MB on a 32-bit data bus out of 8 chips, you have 4Mx4 parts. TMK nobody made a 2 Mbit x 4 DRAM chip, since it still requires 10 address lines, but in a degenerate arrangement).
As long as the support logic in the chip can identify the size correctly (and consequently is able to direct the CAS signals to the correct bank based on the physical address) and the 10 address lines are indeed brought to the pads for the Bank A memory, it ought to work. You said this is the same support chip used in a less compromised system, so it'd be surprising if it didn't work.
As long as the support logic in the chip can identify the size correctly (and consequently is able to direct the CAS signals to the correct bank based on the physical address) and the 10 address lines are indeed brought to the pads for the Bank A memory, it ought to work. You said this is the same support chip used in a less compromised system, so it'd be surprising if it didn't work.
Ah. I just realized you're referring to the DRAMs as 2 megabyte chips, which I suppose is technically correct, as their total capacity when measured in 8-bit bytes is 2048 KB. But this is a misleading designation, because there are other--incompatible--ways to get a 2 megabyte DRAM, such as 1 Mbit x 16.
Part number HYB514100BJ-60
Category
Description 4M X 1bit DRAM
Company Infineon Technologies Corporation
Datasheet Download HYB514100BJ-60 datasheet
Request For Quote Find where to buy HYB514100BJ-60
Category
Description 4M X 1bit DRAM
Company Infineon Technologies Corporation
Datasheet Download HYB514100BJ-60 datasheet
Request For Quote Find where to buy HYB514100BJ-60
Uni, did you try the IIsi using the Vampire Video for the test? If, so slap a Pivot card in there, unhook the cable from the onboard connector and test again.
Done that way, you ought to have a much better chance of it working.
edit: I finally put the probes onto the memory pins of both banks and MDU.
MoBo powered down:
_____74ALS245 buffers at rest
__________Bank_B_pin_4_A0 -> MDU_pin_70
__________Bank_A_pin_6_A0 -> MDU_pin_69
So Bank A Addressing is indeed separate from Bank B Addressing with the buffering ICs in this state.
Can I safely add power from an outside source to the 74ALS245 bus buffer ICs to test the other two states? Individually or separately? Alternately, I could remove de-solder/isolate/power up the VCC leg of the appropriate 74ALS245 a/o DRAM IC? Most radical approach would be to desolder the and 7fALS245 and build a test circuit board with an old school 74LS245?
edit: Does anyone have a link to such a DIY bus testing circuit board, such would be a tremendous help in ferreting out the address and control lines for the 2300c and 1400 for the Video and PCMCIA hacks. [] ]'>
Done that way, you ought to have a much better chance of it working.
edit: I finally put the probes onto the memory pins of both banks and MDU.
MoBo powered down:
_____74ALS245 buffers at rest
__________Bank_B_pin_4_A0 -> MDU_pin_70
__________Bank_A_pin_6_A0 -> MDU_pin_69
So Bank A Addressing is indeed separate from Bank B Addressing with the buffering ICs in this state.
Can I safely add power from an outside source to the 74ALS245 bus buffer ICs to test the other two states? Individually or separately? Alternately, I could remove de-solder/isolate/power up the VCC leg of the appropriate 74ALS245 a/o DRAM IC? Most radical approach would be to desolder the and 7fALS245 and build a test circuit board with an old school 74LS245?
edit: Does anyone have a link to such a DIY bus testing circuit board, such would be a tremendous help in ferreting out the address and control lines for the 2300c and 1400 for the Video and PCMCIA hacks. [
] ]'>
Er, no, 8 4Mx1 chips isn't going to work for bank A in a IIsi. You have installed an 8-bit wide memory; 24 data lines are not connected to anything, even assuming the rest of the pinout is the same (which I doubt).
I've been posting too late at night and some of the other things I wrote about required address bits and memory sizes are not correct, because I was not keeping sets of facts straight. I'd start writing one thing and finish writing another. I should probably unwind it and write a correction.
I've been posting too late at night and some of the other things I wrote about required address bits and memory sizes are not correct, because I was not keeping sets of facts straight. I'd start writing one thing and finish writing another. I should probably unwind it and write a correction.
That would be great, thanks for your help, bear. I've been doing the same late night thing, but early AM as well . . .
. . . burnin' away at both ends of the candle. :-/
We've also got discussions about these DRAM ICs going in two other threads, one about the IIsi, like my questions in this thread and and about the Q605/LC475 in the other. Makes for a nice mess!
. . . burnin' away at both ends of the candle. :-/
We've also got discussions about these DRAM ICs going in two other threads, one about the IIsi, like my questions in this thread and and about the Q605/LC475 in the other. Makes for a nice mess!
OK, I've got a request for help with buzzing a csome connections an one of the two machines I don't have that use the MDU Memory Controller ASIC:
on the IIci & SE/30 there will be a square, 128pin, Quad Flat Pack IC between the CPU and Memory Banks A&B, that's MDU
Pin 17 of MDU is connected to pin 19 on the SIMMs in Bank B - RA10
Pin 16 of MDU is connected to pin 19 on the SIMMs in Bank A - A10 - Yes or NO?
Pin 13 of MDU is connected to pin 24 on the SIMMs in Bank B - RA11
Pin 12 of MDU is connected to pin 24 on the SIMMs in Bank A - A11 - Yes or NO?
WAG:
Please check to see if pins 4,5,8 and 9 of MDU are connected to anything in either SIMM Bank and if so what pins?
Anybody got a hopelessly DOA IIci or SE/30 board to trade for some trinket in my hoard? [
)] ]'>
on the IIci & SE/30 there will be a square, 128pin, Quad Flat Pack IC between the CPU and Memory Banks A&B, that's MDU
Pin 17 of MDU is connected to pin 19 on the SIMMs in Bank B - RA10
Pin 16 of MDU is connected to pin 19 on the SIMMs in Bank A - A10 - Yes or NO?
Pin 13 of MDU is connected to pin 24 on the SIMMs in Bank B - RA11
Pin 12 of MDU is connected to pin 24 on the SIMMs in Bank A - A11 - Yes or NO?
WAG:
Please check to see if pins 4,5,8 and 9 of MDU are connected to anything in either SIMM Bank and if so what pins?
Anybody got a hopelessly DOA IIci or SE/30 board to trade for some trinket in my hoard? [
)] ]'>
Trag basically wrote the correction post I was writing, and beat me to posting it. It's in the Q605 thread.
Yep, but I'm not trying to beef up Bank A on the MoBo at that location.
I'm making adapters to install four double banked 72-pin SIMMs in the slots of Bank B. The first bank of the 32MB, 72 pin SIMM will act as a 16MB 30-pin SIMM in bank B as "usual." The second Bank of each will act as a 16MB 30-pin SIMM in Bank A as in an SE/30.
Since the CPU/MDU can only address Bank B or Bank A on any given cycle, I need to figure out how to multiplex the address and control lines on the adapter using an existing or synthesized Bank Select signal on each of the four adapter. I'm working out how to get around the Vampire Video's Data Line buffering next.
Next to worst case will be implementation of a fifth circuit board multiplexing all the Bank A signals and reflecting them back at the SIMM slots of Bank B.
Worst case would be not being able to get Bank A to work on the adapters in the IIsi, winding up with a way to make inexpensive 16MB SIMMs for Bank B and to max out my Quadra 950 without going broke in the process.
Dunno, but the ersatz Memory line layout/fleshed out Memory schematic I'm building in Illustrator for the project is a pretty neat exercise for learning a bit about Memory Subsystems!)
I'm making adapters to install four double banked 72-pin SIMMs in the slots of Bank B. The first bank of the 32MB, 72 pin SIMM will act as a 16MB 30-pin SIMM in bank B as "usual." The second Bank of each will act as a 16MB 30-pin SIMM in Bank A as in an SE/30.
Since the CPU/MDU can only address Bank B or Bank A on any given cycle, I need to figure out how to multiplex the address and control lines on the adapter using an existing or synthesized Bank Select signal on each of the four adapter. I'm working out how to get around the Vampire Video's Data Line buffering next.
Next to worst case will be implementation of a fifth circuit board multiplexing all the Bank A signals and reflecting them back at the SIMM slots of Bank B.
Worst case would be not being able to get Bank A to work on the adapters in the IIsi, winding up with a way to make inexpensive 16MB SIMMs for Bank B and to max out my Quadra 950 without going broke in the process.
Dunno, but the ersatz Memory line layout/fleshed out Memory schematic I'm building in Illustrator for the project is a pretty neat exercise for learning a bit about Memory Subsystems!
)
30pinMESS.2p.jpg[/attachment]
. . . much work to be done on the blocking diagram of the Bank A end of things before I can make any real progress on the adapter end. :
. . . much work to be done on the blocking diagram of the Bank A end of things before I can make any real progress on the adapter end. :
Holy crap!!!!! 8-o
[attachment=0]SSIMM_pinout_comparison.2p.jpg[/attachment]
No wonder the industry switched over to 72-pin SIMMs ASAP! :
[attachment=0]SSIMM_pinout_comparison.2p.jpg[/attachment]
No wonder the industry switched over to 72-pin SIMMs ASAP! :