Thread
Memory Addressing Questions
I guess if you keep banging your idiotic head on the 22" CRT you can finally get somewhere . . .
of[/i] the SE/30 :-/ >
of[/i] the SE/30 :-/ >
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More questions:
Since both Bank A and Bank B run their data lines through the 245s, I'm WAGgin' that I'll need to create a similar circuit inside the illustrated box to Buffer the Address and Control lines and a Bank select signal just like the Data lines are currently gated?
Such a circuit will need to multiplex the address and control lines on the MoBo between Bank B (and my ersatz Bank A converters) to reflect the Bank A lines back over to the disconnected "Bank B" on the 72 pin SIMMs through the existing traces on the MoBo?
I may need to similarly hack the Data Line buffering to work from my relocated "Bank A" as well.
Does any of this make sense to someone? :-/
Since both Bank A and Bank B run their data lines through the 245s, I'm WAGgin' that I'll need to create a similar circuit inside the illustrated box to Buffer the Address and Control lines and a Bank select signal just like the Data lines are currently gated?
Such a circuit will need to multiplex the address and control lines on the MoBo between Bank B (and my ersatz Bank A converters) to reflect the Bank A lines back over to the disconnected "Bank B" on the 72 pin SIMMs through the existing traces on the MoBo?
I may need to similarly hack the Data Line buffering to work from my relocated "Bank A" as well.
Does any of this make sense to someone? :-/
Guess not . . . whatever! :lol:
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[attachment=0]Octal_FlipFlop-or-NOR.2p.jpg[/attachment]
Quick question, 74LSXXXX was a long time ago. :/
Do I want to replace the 245s with which choice in the caption or another type to send the Bank A Data Signals back over the Bank B traces?
I'm figuring on using W/E as my bank select and a nasty hack for getting the addressing for bank A to the adapter's Banks at Bank B.
The tiny purple txt and arrows shows where the bank A Data Lines go with the 75ALS245s that need to be replaced to multiplex the Data Lines.
Quick question, 74LSXXXX was a long time ago. :/
Do I want to replace the 245s with which choice in the caption or another type to send the Bank A Data Signals back over the Bank B traces?
I'm figuring on using W/E as my bank select and a nasty hack for getting the addressing for bank A to the adapter's Banks at Bank B.
The tiny purple txt and arrows shows where the bank A Data Lines go with the 75ALS245s that need to be replaced to multiplex the Data Lines.
Hrmmm . . . no suggestions? I really could use some help on the 74ALS245 Buffer IC replacements. :-/
Here's the fugly address line multiplexing hack as it now stands:
MDU Cannot Address Banks A & B simultaneously, nor can it read data from A & B simultaneously (see crude Data Line multiplexing hack above.)
All the address lines for Banks A & B are very conveniently located right next to each other on MDU.
Using Diodes (like backflow valves in plumbing) soldered to the lifted legs of the paired Banks A & B Address signals on MDU, the diodes are then soldered/shorted together and the paired signals are soldered to the disconnected pads of all twelve Address lines heading to the Bank B SIMM Slots. The Banks A & B addressing signals are multiplexed on the Bank B traces by the either/or logic of MDU's limited Address and Data line capabilities.
Add those discrete 24 addressing signals multiplexed over the MoBo's Bank B traces to the 64 discrete Data Lines for Banks A & B multiplexed over the MoBo traces for Bank B and I'm down to a very limited number of Bank A control lines left to hack. I haven't looked at it yet, but I haven't come up with any obvious reason why I shouldn't be able to do the same Diode-Short Multiplexing for the diccrete(?) RAS and CAS lines for banks A & B.
If I can get it down to where I only need to run signals over two patch wires to the two n.c. pins of the 30-pin SIMM spec. I'll be happy!
But if I can get it down to patching just the W/E signal for the Bank A DRAM ICs to just one of those n.c. pins to select the Bank A halves of my adapters for the Double Banked 32MB 72-pin SIMMs while MDU is not enabling same for Bank B for the reasons outlined above, that'd be just about perfect! [}
] ]'>
Would somebody PLEASE check out the assumptions I've made above and let me know if this craziness is possible . . .
. . . must I be missing something here? :lol:
Here's the fugly address line multiplexing hack as it now stands:
MDU Cannot Address Banks A & B simultaneously, nor can it read data from A & B simultaneously (see crude Data Line multiplexing hack above.)
All the address lines for Banks A & B are very conveniently located right next to each other on MDU.
Using Diodes (like backflow valves in plumbing) soldered to the lifted legs of the paired Banks A & B Address signals on MDU, the diodes are then soldered/shorted together and the paired signals are soldered to the disconnected pads of all twelve Address lines heading to the Bank B SIMM Slots. The Banks A & B addressing signals are multiplexed on the Bank B traces by the either/or logic of MDU's limited Address and Data line capabilities.
Add those discrete 24 addressing signals multiplexed over the MoBo's Bank B traces to the 64 discrete Data Lines for Banks A & B multiplexed over the MoBo traces for Bank B and I'm down to a very limited number of Bank A control lines left to hack. I haven't looked at it yet, but I haven't come up with any obvious reason why I shouldn't be able to do the same Diode-Short Multiplexing for the diccrete(?) RAS and CAS lines for banks A & B.
If I can get it down to where I only need to run signals over two patch wires to the two n.c. pins of the 30-pin SIMM spec. I'll be happy!
But if I can get it down to patching just the W/E signal for the Bank A DRAM ICs to just one of those n.c. pins to select the Bank A halves of my adapters for the Double Banked 32MB 72-pin SIMMs while MDU is not enabling same for Bank B for the reasons outlined above, that'd be just about perfect! [}
] ]'>Would somebody PLEASE check out the assumptions I've made above and let me know if this craziness is possible . . .
. . . must I be missing something here? :lol:
Are the diodes really necessary to buffer the address signals for Banks A & B outputs from MDU.? My original notion was to simply short the two legs together, but I figured having chip driving signals shove back into outputs of an ASIC would probably be a BAD THING.
Is there a convenient little three SMT "nubbin" equivalent of the twisted pairs in the proposed the old school Diode Radio Antenna Farm illustration?
note: I know it's silly (at best) to obsess on getting this project to work, I've already got the Radius Rocket with its onboard compliment of 128MB of interleaved PC SIMMs hacked into the SuperIIsi™ but this proposition is just too delicious to ignore.
If I can get the IIsi to work with the Radius Color Pivot II/IIsi replacing Vampire Video and this hack implemented as planned, I might be able to overclock a IIsi to the point that it outperforms a IIci at its overclocked best. Dunno, but it's yet another fascinating evolution in "tilting at windmills" of the retro-computing world of Apple's hamstrung LEM lineup. [}] ]'>
Is there a convenient little three SMT "nubbin" equivalent of the twisted pairs in the proposed the old school Diode Radio Antenna Farm illustration?
note: I know it's silly (at best) to obsess on getting this project to work, I've already got the Radius Rocket with its onboard compliment of 128MB of interleaved PC SIMMs hacked into the SuperIIsi™ but this proposition is just too delicious to ignore.
If I can get the IIsi to work with the Radius Color Pivot II/IIsi replacing Vampire Video and this hack implemented as planned, I might be able to overclock a IIsi to the point that it outperforms a IIci at its overclocked best. Dunno, but it's yet another fascinating evolution in "tilting at windmills" of the retro-computing world of Apple's hamstrung LEM lineup. [}
] ]'>
Thats why you should use an OR gate. If either pin goes high, the output goes high.
Yep, but the way the bank addressing works, they can't both go high at the same time because the Mac and MDU cannot address both banks at once. The OR logic for bank addressing is already built into MDU ASIC to begin with.
Am I incorrect in that observation?
The W/E lines control which DRAM ICs on either 16MB side of the double-banked, double sided 72-pin SIMM will be active and which inactive at that end of the traces.
Am I incorrect in that observation?
The W/E lines control which DRAM ICs on either 16MB side of the double-banked, double sided 72-pin SIMM will be active and which inactive at that end of the traces.