Thread
Q605/LC475 (onboard) ram upgrade.
Were the onboard chips 80ns and the chips on your SIMM 60ns? Would something like that explain the speed boost?
I found an auction for a 16MB 30-pin simm, read the part number off the Siemens chips on it, did a little googling, and found this auction for just the chips themselves ($2 each in lots of 25). I'd be happy to split the cost of one lot with you if you want to try! (It's a "best offer" auction, so maybe we can get the price down some.)
Only possible snag: the chips in that auction are 50ns, while the fastest RAM I've ever heard of in a 30 or 72-pin SIMM for Mac was 60ns. Any reason a 475/605 couldn't handle the faster 50ns RAM?
144MB would be so gross!
)
I found an auction for a 16MB 30-pin simm, read the part number off the Siemens chips on it, did a little googling, and found this auction for just the chips themselves ($2 each in lots of 25). I'd be happy to split the cost of one lot with you if you want to try! (It's a "best offer" auction, so maybe we can get the price down some.)
Only possible snag: the chips in that auction are 50ns, while the fastest RAM I've ever heard of in a 30 or 72-pin SIMM for Mac was 60ns. Any reason a 475/605 couldn't handle the faster 50ns RAM?
144MB would be so gross!
) i was thinking about that…
(and that might be some of whats going on)
My theory is more that the memory controller has to ASINC the memory bus in order to use that stupid 4megs of slow old ram.
With that 4mb's not on there… the memory controller switches to synchronous mode. with a full pipe to the 72 pin simm…
The 24 pin ram might be faster ram all the way around… not in just NS.
I think that 20pin ram is old… and was thrown on there to save money and to give the customer a value added feature of some onboard ram.
after all the LC475 and Q605 WERE value added machines…. not performance…
So yeah i am saying the memory controller directly allowing greater performance.
Not having to slow everything down as the same speed is the S**T 4megs onboard.
I have no wiggle room in my budget.. -- and i have no idea as if those ram chips will work.
-- i do see they are 20pin… and i'm sure that is good… but other then that i have no idea… and no $$ budget.
-- i am almost thinking populating that spot with any 20pin ram chip is just going to slow the system back down….
WITCH leads me to now be more interested in trash80's idea
viewtopic.php?f=29&t=22643
he's probably on to something … Yeah … for sure…!
because 256 megs of ram in a LC475/Q605 would be more sick…
using 2 matchings simms with all 24 pin chips….
i think we need to look up a data sheet on the memory controller…. we might have found out its greater capabilities
----silly apple purpously slowing down our computers on us!!!!!!!!!!!!!!!!
this was from here: viewtopic.php?f=9&t=15958
I guess this is good info for both of my threads… anything to help the cause.
I love the way you took my grandiose schemes for the IIsi and came up with your own plans, attacking it from the IC side of Bank A there and for the Q605/LC475 here. You don't need to credit me for the IIsi idea. Great work there, uni!
The info in the thread you linked to is much more applicable to the 605, not so much the LC475. The MicroQuadraFeetsMac™ has handy, removable ribs hidden within the deeper, flat-n-feeted case. I posted the riddles/info in the IIsi thread to help, definitely not brag, I didn't want to steal any volume from your thunderous achievements. I love collaborating on a hack from multiple fronts. My back-burnered hacks would likely never be realized otherwise . . .
. . . now you can work out the mapping for 320MB or 512MB of 72-pin SIMMs in the 605! }
Removing the ICs from Bank A is a great start, BTW. De-solder the thru-holes for the unimplemented ROM SIMM for routing your jumper wires. and take the hack underboard/subterranean/fairly stealth, as I'm doing an under the board IIsi PDS hack. Only you won't have to cut a hole in the bottom if you use flat 72 pin SIMM Sockets or just solder them directly to the PCB at a very low angle . . .
. . . its not like you'll ever really need to upgrade the RAM again! :lol:
I'm glad you started this project, it gave me a big kick in the butt on a lost hack. I'd posted it by mistake in 68k LC & Performa instead of Mac II, Quadra & Centris for folks interested in the 605 might take note of it. I guess it really belongs here in Hacks & Development. I found it only by searching for the IIsi info, it never made it onto the crib-sheet topic I made for my projects.
The info in the thread you linked to is much more applicable to the 605, not so much the LC475. The MicroQuadraFeetsMac™ has handy, removable ribs hidden within the deeper, flat-n-feeted case. I posted the riddles/info in the IIsi thread to help, definitely not brag, I didn't want to steal any volume from your thunderous achievements. I love collaborating on a hack from multiple fronts. My back-burnered hacks would likely never be realized otherwise . . .
. . . now you can work out the mapping for 320MB or 512MB of 72-pin SIMMs in the 605! }
Removing the ICs from Bank A is a great start, BTW. De-solder the thru-holes for the unimplemented ROM SIMM for routing your jumper wires. and take the hack underboard/subterranean/fairly stealth, as I'm doing an under the board IIsi PDS hack. Only you won't have to cut a hole in the bottom if you use flat 72 pin SIMM Sockets or just solder them directly to the PCB at a very low angle . . .
. . . its not like you'll ever really need to upgrade the RAM again! :lol:
I'm glad you started this project, it gave me a big kick in the butt on a lost hack. I'd posted it by mistake in 68k LC & Performa instead of Mac II, Quadra & Centris for folks interested in the 605 might take note of it. I guess it really belongs here in Hacks & Development. I found it only by searching for the IIsi info, it never made it onto the crib-sheet topic I made for my projects.
not sure buddy.
- on the ram simm chip swap idea.
I got a boat load o work to do so, any benches for now, gotta wait.
If I had to throw out a number, I would say, feels like 20% better w/o that 4 megs on there bringing it down.
the difference seemed more significant when booted up Max Rez, the only other thing, at max rez, you only have 256 colors.
that might be less desirable for some.
Seems to me 20 pin ram is more likely on the older 30pin simms…
and the 24pin chips are mostly on the newer 72pin simms.
So i think its entirely likely that, the 4mb on there is handy capping the performance.
* maybe by design *
- on the ram simm chip swap idea.
I got a boat load o work to do so, any benches for now, gotta wait.
If I had to throw out a number, I would say, feels like 20% better w/o that 4 megs on there bringing it down.
the difference seemed more significant when booted up Max Rez, the only other thing, at max rez, you only have 256 colors.
that might be less desirable for some.
Seems to me 20 pin ram is more likely on the older 30pin simms…
and the 24pin chips are mostly on the newer 72pin simms.
So i think its entirely likely that, the 4mb on there is handy capping the performance.
* maybe by design *
ok i just did a real quick test Video and CPU only
- 605 is w/o the 4megs of ram.
- 605-w-4mb is acutely the really nice LC475 i got from mcdermd
(both OC'd)
I ran the test then i pulled out the ram and hd, installed into the other machine.
ok so the 605 w/o 4meg ram (Video benchmark) is the same as the Quadra 950 (127)
the 605 /w 4megs is (105)
the CPU is a little different too. but not much.
w/o 4mb ram is (130)
/w 4mb is (128)
[attachment=1]Screen Shot 2013-12-29 at 8.18.22 PM.png[/attachment]
[attachment=0]Screen Shot 2013-12-29 at 8.18.32 PM.png[/attachment]
- 605 is w/o the 4megs of ram.
- 605-w-4mb is acutely the really nice LC475 i got from mcdermd
(both OC'd)
I ran the test then i pulled out the ram and hd, installed into the other machine.
ok so the 605 w/o 4meg ram (Video benchmark) is the same as the Quadra 950 (127)
the 605 /w 4megs is (105)
the CPU is a little different too. but not much.
w/o 4mb ram is (130)
/w 4mb is (128)
[attachment=1]Screen Shot 2013-12-29 at 8.18.22 PM.png[/attachment]
[attachment=0]Screen Shot 2013-12-29 at 8.18.32 PM.png[/attachment]
I bet the speed of the on-board RAM is extremely slow, So of course when you expand it, its still running at the speed of the on-board RAM.
Kinda like mixing DDR400 with DDR266. it runs at 266.
Which is precisely why when you remove the RAM, or replace the RAM with faster RAM on-board, it speeds up tremendously.
Kinda like mixing DDR400 with DDR266. it runs at 266.
Which is precisely why when you remove the RAM, or replace the RAM with faster RAM on-board, it speeds up tremendously.
The memory controller on the 605 supports interleaving, but the 4mb of onboard ram is not interleaved because it is just 4mb in a single bank.
The RAM SIMM will nearly always span banks and therefore be interleaved. Interleaving can give up to 10-15% speed improvement depending on how it is being accessed.
The onboard video will always come from the onboard RAM (if there is any), so it will always use the "slower" RAM.
You can also see this on the Centris/Quadra 610 and 650's. If you get one with 4mb soldered, it'll be non-interleaved, and if you get one with 8mb soldered, that'll be interleaved and therefore faster.
The RAM SIMM will nearly always span banks and therefore be interleaved. Interleaving can give up to 10-15% speed improvement depending on how it is being accessed.
The onboard video will always come from the onboard RAM (if there is any), so it will always use the "slower" RAM.
You can also see this on the Centris/Quadra 610 and 650's. If you get one with 4mb soldered, it'll be non-interleaved, and if you get one with 8mb soldered, that'll be interleaved and therefore faster.
JFYI, with the 610 series, you can't interleave RAM SIMMs because of the way they arranged the banks. It has half the SIMM slots, and rather than just leaving off the top 2 SIMMs, they've split things up so every other bank will be empty, preventing any interleaving of the SIMM slots. 8mb soldered is still interleaved, but the SIMM slots are gimped.
I never thought much of the 650 and 800 machines until I started messing with the memory controller. Now, they're pretty much my favorite 040's. Solder on a ROM SIMM slot, put a modified ROM on there to disable the RAM check and enable the 128mb SIMMs, and just have fun with a ~300MB RAM disk.
I never thought much of the 650 and 800 machines until I started messing with the memory controller. Now, they're pretty much my favorite 040's. Solder on a ROM SIMM slot, put a modified ROM on there to disable the RAM check and enable the 128mb SIMMs, and just have fun with a ~300MB RAM disk.
lol how do you enable 128meg simms for the q800?
also can you be so kind as to pm me with that bin
awesome man!
but not through the rom slot holes.
with 512 megs of ram in a q605,,,,,,,,,,,,,,,,,,,,, we will need to disable the ram test for sure!
-- so the rom slot will be needed for sure. ( and a special bin )
if someone were to accomplish this… it would be the Mac HAC of 2014
does bbraun want to take this on is the question
?
also can you be so kind as to pm me with that bin
awesome man!
yeah that would be pretty bad-ass to epoxy a 72pin simm slot to the bottom of the PCB and run some wiresTrash80 - The 605's removable ribs hidden within the deeper, flat-n-feeted case. I posted the riddles/info in the IIsi thread to help, definitely not brag, I didn't want to steal any volume from your thunderous achievements. I love collaborating on a hack from multiple fronts. My back-burnered hacks would likely never be realized otherwise . . .. . . now you can work out the mapping for 320MB or 512MB of 72-pin SIMMs in the 605! }
but not through the rom slot holes.
with 512 megs of ram in a q605,,,,,,,,,,,,,,,,,,,,, we will need to disable the ram test for sure!
-- so the rom slot will be needed for sure. ( and a special bin )
if someone were to accomplish this… it would be the Mac HAC of 2014
does bbraun want to take this on is the question
?Nope, you'd be soldering the SIMMs to an adapter PCB soldered/socketed directly to the MoBo, nestled between the remaining ribs of the intact bottom surfaced case.yeah that would be pretty bad-ass to epoxy a 72pin simm slot to the bottom of the PCB and run some wiresTrash80 - The 605's removable ribs hidden within the deeper, flat-n-feeted case . . .. . . now you can work out the mapping for 320MB or 512MB of 72-pin SIMMs in the 605! }
Who said anything about not using a ROM SIMM, just move that to the adapter to make room for most of the wires, it sits on part of the same address/data/control line bus as the RAM, with a few ROM specific signals added, IIRC. Voila! Holes to spare! [}
] ]'>I hope he decides to get involved in this as well, I'm working out the funneling issues for using inexpensive 72-pin SIMMs already, albeit v-e-r-y slowly! :if someone were to accomplish this… it would be the Mac HAC of 2014
How about soldering a SIMM socket where the on board chips were?
I suppose it would have to be surface mount, but it could be done, couldn't it?
It would be a bit messier looking, I suppose, but more easily removable (and perhaps even a bit more reliable, since the extra length of the wires going underneath could do bad things to the signals running through).
c
I suppose it would have to be surface mount, but it could be done, couldn't it?
It would be a bit messier looking, I suppose, but more easily removable (and perhaps even a bit more reliable, since the extra length of the wires going underneath could do bad things to the signals running through).
c
What about the Q630/LC580? It has 4MB soldered on too, and is frankly a more full-featured platform (IDE, CommSlot, Video in/out) than the 605 or 575 boards. Has anybody tried a 128MB SIMM in there? Any reason to believe it would work any differently?
I'll have to snag my dad's 63x from his office at work and get it to Uni for recapping/experimenting.
I'll have to snag my dad's 63x from his office at work and get it to Uni for recapping/experimenting.
Funny you should mention the 630, I've been working from that DevNote this afternoon.
Curiously, it says the Q630 family came with either 4MB or 8MB on the MoBo and support for a double banked 32MB SIMM. However the Max Memory configs are listed and graphed/mapped as having a 36MB ceiling. I don't know where a 128MB SIMM might fit into that scheme, but the DevNote specifically states the 630's incompatibility with 64MB SIMMs.
I'm not sure where the TWO SIMM Slotted DOS Compatibles fit into that scheme?
_____Did they have DRAM soldered to the MoBo?
_____Did they eschew onboard RAM in order to address a pair of double banked SIMMs as four banks of RAM?
Curiouser and curiouser . . . :?:
edit: ISTR more memory being used in the 630, be that as it may:
I missed part of one page, but . . .
[attachment=3]Q630mem_A.jpg[/attachment]
[attachment=2]Q630mem_B.jpg[/attachment]
[attachment=1]Q630mem_C.jpg[/attachment]
[attachment=0]Q630mem_D.jpg[/attachment]
. . . zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz |)
Curiously, it says the Q630 family came with either 4MB or 8MB on the MoBo and support for a double banked 32MB SIMM. However the Max Memory configs are listed and graphed/mapped as having a 36MB ceiling. I don't know where a 128MB SIMM might fit into that scheme, but the DevNote specifically states the 630's incompatibility with 64MB SIMMs.
I'm not sure where the TWO SIMM Slotted DOS Compatibles fit into that scheme?
_____Did they have DRAM soldered to the MoBo?
_____Did they eschew onboard RAM in order to address a pair of double banked SIMMs as four banks of RAM?
Curiouser and curiouser . . . :?:
edit: ISTR more memory being used in the 630, be that as it may:
I missed part of one page, but . . .
[attachment=3]Q630mem_A.jpg[/attachment]
[attachment=2]Q630mem_B.jpg[/attachment]
[attachment=1]Q630mem_C.jpg[/attachment]
[attachment=0]Q630mem_D.jpg[/attachment]
. . . zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz |)
The 630 can take up to a 128mb SIMM in a 32x32 configuration, I believe. The second simm slot, on boards that have it, can only take up to 64mb (I think you need to use the 128mb SIMM, and only 64 of that is visible). There's several threads about it, and trag has described the SIMMs to use. It should be the same 128mb simms that work in the 605.What about the Q630/LC580? It has 4MB soldered on too, and is frankly a more full-featured platform (IDE, CommSlot, Video in/out) than the 605 or 575 boards. Has anybody tried a 128MB SIMM in there? Any reason to believe it would work any differently?I'll have to snag my dad's 63x from his office at work and get it to Uni for recapping/experimenting.
hey there i thought i would update everyone i tried this ram in the q605, and it doesn't work.
gets the bong, sits there.
no video…
remove the ram .. and bong + video… i even noticed some of the ram chips are 50ns and 60ns… i had installed them mixed… i even removed all the 50ns chips so all 60ns chips are there.
so anyways these 2m per chip ones do not work in the LC475/605
[attachment=0]Screen Shot 2014-01-15 at 1.05.50 AM.png[/attachment]
worth a try but doesn't work… i am going to try it in the iisi … but i am rather doubtful it will work…
but will try it in the iisi to see if it works in there...
gets the bong, sits there.
no video…
remove the ram .. and bong + video… i even noticed some of the ram chips are 50ns and 60ns… i had installed them mixed… i even removed all the 50ns chips so all 60ns chips are there.
so anyways these 2m per chip ones do not work in the LC475/605
[attachment=0]Screen Shot 2014-01-15 at 1.05.50 AM.png[/attachment]
worth a try but doesn't work… i am going to try it in the iisi … but i am rather doubtful it will work…
but will try it in the iisi to see if it works in there...
What was the speed or the original? I know RAM speed is not normally an issue, but there is an old thread and recent conversation on this very issue. In a Plus RAM running too fast caused issues. It should not, but ya never know.
Just my 2 cents. You guys know a lot more about this stuff than I do.
Just my 2 cents. You guys know a lot more about this stuff than I do.
yeah sorry it doesn't work in the IIsi ether.
but the good news is, now that i have the heat gun and the hot air re-flow fired up i decided to upgrade my other IIsi to 4 megs of ram from my q605…
and if MinerAI is nice enough to give me the 4 megs from his q605 lol …. i will have 3 IIsi's with 4 megs onboard!! …
BETTER THEN nothin!
.
but the good news is, now that i have the heat gun and the hot air re-flow fired up i decided to upgrade my other IIsi to 4 megs of ram from my q605…
and if MinerAI is nice enough to give me the 4 megs from his q605 lol …. i will have 3 IIsi's with 4 megs onboard!! …
BETTER THEN nothin!
.
Bummer about these chips being the wrong flavor to work with these Macs. But now you have 25 little decorative baubles. Try making jewelry out of them!
Just to be clear these chips were: SIEMENS HYB514100BJ, which is a "4M x 1 Bit FPM DRAM 5V 60ns chip." RAM gurus: what is it about this RAM chip that is incompatible with the Macs? Is it the 4M x 1 part? For what kind of chip should we be looking?
There's an auction for 16MB SIMMs that are supposed to work with SE/30s and have eight NEC 4216100-60 chips on them. If they work in an SE/30 can we assume they will work in another Mac? Are those the kinds of chips we should be searching for?
Just to be clear these chips were: SIEMENS HYB514100BJ, which is a "4M x 1 Bit FPM DRAM 5V 60ns chip." RAM gurus: what is it about this RAM chip that is incompatible with the Macs? Is it the 4M x 1 part? For what kind of chip should we be looking?
There's an auction for 16MB SIMMs that are supposed to work with SE/30s and have eight NEC 4216100-60 chips on them. If they work in an SE/30 can we assume they will work in another Mac? Are those the kinds of chips we should be searching for?
I just looked at my RAM. I have 16MB 30 pin modules I just picked up for some hardware I have coming Friday. 8 chips on one side only. Like the auction you linked, mine have groupings of 6 pins (24 pins total) versus 20 pins total like you soldered on. I assume that the extra pins will be an issue?
whats funny is the chips we already have… were on 16 meg 30pin simms already, corect?
not going to lie, all that work and almost no progress really bummed me out.
but i am still willing to try different chips if anyone has some that we can make a better hypothesis on…
ok… so is there a reason apple used 4 meg? i mean the q700 / LC3's lc2's / 610 / 605…. even the powermac 6100… that has 2 banks of 4 meg to make 8… but same chips.
are we sure apple just didn't maybe buy like a million of these ram chips and tried to maximize their use across many models?
so they might have something in the memory controller that is only going to accept a 4 megs….
and with the IIsi we were just lucky… maybe they were going to put 4 megs in there anyways… that might be why it works…
not going to lie, all that work and almost no progress really bummed me out.
but i am still willing to try different chips if anyone has some that we can make a better hypothesis on…
ok… so is there a reason apple used 4 meg? i mean the q700 / LC3's lc2's / 610 / 605…. even the powermac 6100… that has 2 banks of 4 meg to make 8… but same chips.
are we sure apple just didn't maybe buy like a million of these ram chips and tried to maximize their use across many models?
so they might have something in the memory controller that is only going to accept a 4 megs….
and with the IIsi we were just lucky… maybe they were going to put 4 megs in there anyways… that might be why it works…
The Q605/LC/P475/476 has separate video RAM SIMMs, so the onboard system RAM is not used for video. Most likely your interleaving information is the relevant fact in this case.
Remember that the Quadras need 32 bit wide memory. So your eight memory chips must be 4 bits wide each, in order to supply 32 bits per read or write operation.
If the capacity of the chips is 512KB each (4 MB divided by eight chips) then each chip must have 1024K addresses. Or another way to look at it is that a 512KB chips is the same as a 4Mb(it) chip, and if it provides four bits at a time, then it must be 1M (1024K) X 4 bits.
1M of address space is 20 bits of addressing. Operations with RAM memory are performed with multiplexed addresses, in which the address bits are split into Row and Column segments. So, this memory is likely to be 10 X 10 X 4 bits. 10 row address bits, by 10 column address bits by 4 data bits. Although it could be 11 X 9 or some such.
So let's do a pin count. Each chip has 4 data bits, (at least) 10 address bits, and RAS, CAS and WE control lines. Additionally, there must be at least one GND and one Vcc line per chip. I think there might be an OE_ pin as well. That's 20 pins per chip.
You want a larger capacity RAM chip in the same 20 pin package, but it simply isn't possible. Any RAM chip you can use must have the same 4 data bits/pins, the same RAS, CAS, WE and OE control lines. At least one GND and VCC line. That only leaves 10 pins out of the twenty. Ten address pins gives you 10 row + 10 column address bits maximum, which is what you already have.
In order to have a larger capacity memory chip, you must add address lines, which pushes you over 20 pins.
Unfortunately, the chips in that auction are 4M X 1 chips. Eight of them will only provide 8 bits of parallel data, because each of the chips is only providing one bit of data per operation. Those will not work, as Uniserver discovered. He would need to use 4M X 4 chips in order to increase the capacity, but 4M X 4 chips will be 24 or 22 pins. I'm sorry I didn't read this thread sooner. I would have liked to save you the expense.
Probably not. In most cases, the memory controller is programmed (or built) to supply the RAS address, supply the CAS address, and then sample the data lines (or report the transaction complete to the CPU so it can sample the data bus), at a fixed time based on how many cycles the specified RAM can be expected to need to supply (or consume, for writes) the data. So, a computer which needs at least 80 ns RAM will always wait the amount of time in the specification for 80 ns RAM, before assuming that the data is available. If you install faster RAM, the data will appear on the bus sooner, but the memory controller won't know to complete the transaction earlier.
I suppose there could be calibrating memory controllers out there, which would perform a memory performance test at start up to determine what the timing margins are for the RAM, but this would be dangerous, because temperature is likely to affect the timing margins, and so 80 ns RAM might perform like 60 ns RAM at start up, and then slow down to the 80 ns specification when heated. The memory controller doesn't have any way to read the label, nor to know what the temperature is.
Modern RAM, which someone used as an example is a completely different animal. DDR2 memory for example, supplies a DQS signal along with every 4 or 8 bits of data signal. When the DQS signal arrives the memory controller knows that valid read data has also arrived. Similarly in the other direction. The FPM memory used by these old computers has no protocol to signal when the data is really on the bus. This is part of what being non-synchronous means.
The 260 MB Q605 configuration was accomplished with a 72 pin to two 72 pin SIMM doubler, and no, the lid would not close. But it was a proof of concept, not a configuration intended for operation. The two 72 pin SIMMs were the 128 MB SIMMs we are all familiar with.
Don't know if this is possible. There are a couple of issues. First, how much the memory map in the ROM will allow and other ROM issues. Rob is your man for that stuff.well…. 512megs of ram in a q605 would knock MinerAI's socks off.
the couple that with the 42mhz beastly OC…. man…
Second, we know that the main SIMM socket will handle a pair of 128MB SIMMs. I don't know how it does that for certain, but I believe that it (the Q605) must have the ability to control each of the RAS lines in the 72 pin socket (four total) separately.
A 72 pin SIMM bank is limited to 64MB in capacity. That is a hard theoretical limit. Explanation later.
So, the SIMM socket in the Q605 appears to be able to manage 4 banks. How many banks can the circuitry for the soldered RAM manage? It should be able to manage at least one bank of 64 MB (if you add the two address lines), but how many independent RAS lines are present or available? Or are there unused RAS pins on the memory controller chip?
Why a 72 pin SIMM is limited to 64MB per bank:
The 72 pin SIMM specification includes 12 address lines. The address lines are used twice in each memory operation (first one Row address, signaled by the RAS_ control signal, and second one Column address, signaled by the CAS_ control signal).
Twelve addresses times two equals 24 address bits. Twenty-four bits of address gives 2^24 addresses = 16M addresses (slightly more than 16 million).
The 72 pin SIMM is four bytes (32 bits) wide. So every address points at 4 bytes. So, 16M addresses, each pointing at 4 bytes of data, gives 16M X 4 = 64M bytes of capacity.
Banks Later DIMMs have additional address pins labeled "bank" pins but there was no such thing on 72 pin SIMMs. Instead, 72 pin SIMMs have four RAS_ control signals/pins. For a single bank SIMM, only two of the RAS_ lines may be tied together and routed to the RAS_ pins on the memory chips.
However, if one wants a two bank SIMM, then two of the RAS_ lines are tied together and routed to one bank of memory chips, and the other pair of RAS_ lines are tied together and routed to the other bank of memory chips. The RAS signal is always the first control signal associated with any operation, so arranging the SIMM so that a bank of memory chips only gets a RAS signal when it is being used works great as a Bank selection signal.
Of course, the computer using the multi-banked SIMMs must have circuitry/firmware which allows it to control its RAS_ signals one or two or four at a time and understand that doing so addresses separate banks of RAM. So the computer and the SIMM both must agree about how the RAS signals will be used to indicate banks. A really flexible computer can run tests at startup to determine whether a SIMM has more than one bank of memory chips on-board. Such flexibility is probably rare.
From what I've read, the 72 pin standard does not envision the RAS_ lines being used individually, only in pairs, so I'm still puzzled how a pair of 128MB SIMMs worked in a SIMM doubler, but perhaps Apple went off spec. and allowed the RAS to operate independently. Additionally, I could not get 128MB SIMMs to work in the PM6100 even though it supports 64MB SIMMs and two bank SIMMs, suggesting that something is wonky with how Apple associates RAS lines. So there's still some lack in my knowledge about exactly how finely the RAS_ signals can be mixed and matched.
If any of you have a copy of the 72 pin SIMM JEDEC standard kicking around and wants to email it to me, feel free.
Given that the address and data lines are probably common amongst the SIMM sockets, could one just switch which RAS pin is ocnnected to one of the SIMM sockets on the 610 and get interleaving back? If Apple used the same chip set for the 610 as they did for the 650/800, then the pin(s) that control the complementary SIMM sockets are still present, just unused. It should be a relatively minor operation to lift the pin or cut the trace for the existing RAS (and maybe CAS?) signal and run a rework wire from the memory controller's complementary RAS line to the SIMM socket to turn the socket into one which is capable of interleaving with the unmodified socket.
If I ever get the 610 logic board out of the attic again....
I think that I've read of a Japanese fellow doing something like this to the Q605. Pulling up the soldered down RAM and adding a SIMM socket via wires to the board. It would be messy.yeah that would be pretty bad-ass to epoxy a 72pin simm slot to the bottom of the PCB and run some wires
Yes, the part of the Apple Dev, Note which claims that the Q630 will not address 64M SIMMs lies. From what I can gather, the first SIMM socket has two banks available and the second SIMM socket (if present) has only one bank of control available. So the maximum is 64M X 3 (two banks in original SIMM and 1 bank in optional SIMM) plus on-board RAM. It should be possible to expand the on-board to 64MB as well, yielding 256 MB of RAM, but again, that would be messy with wire everywhere, or funny custom circuit boards in the SIMM sockets.
If you got this far and thought it was useful or were bored to tears, please say something. Often, when I post these data dumps they're met with echoing silence. I don't know whether that's because they're not very useful and too long, etc. or because folks just don't feel like there's much left to say afterwards.
It just takes a long time to digest, it gets the gears turning. thank you for the info.
I don't know about anyone else but I have to look and read up so I know what your talking about, because frankly I am not that well versed. I am trying to pick it up but still kind of off the mark for me.
I don't know about anyone else but I have to look and read up so I know what your talking about, because frankly I am not that well versed. I am trying to pick it up but still kind of off the mark for me.
Absolutely, this post is great and I much appreciate everything you've post about memory and everything else. The information you've posted has been the inspiration for at least three of my projects.
I try to assimilate whatever you, bbraun, bmow and now comrade bear post about anything and everything! :approve:
many thanks to all of you,
jt
I try to assimilate whatever you, bbraun, bmow and now comrade bear post about anything and everything! :approve:
many thanks to all of you,
jt
Do the Q605/LC 475 boot w/o the DRAM on the MoBo?
From what trag has said about the limitations of the second SIMM in the 605 and the 630, it makes me wonder if the Mobo RAM is excised these machines might be able to address the full theoretical loadout using the four full capabilities of double banked SIMMs. It appears to me that the MoBo RAM is set up as a hobbled replacement for the first(second?) bank of the extra SIMM and that doing away with the MoBo DRAM ICs might free up those control lines for use on the unaddressable bank of the additional SIMM?
It's still and "under the board" PCB Hack, but what the heck!?! [}] ]'>
From what trag has said about the limitations of the second SIMM in the 605 and the 630, it makes me wonder if the Mobo RAM is excised these machines might be able to address the full theoretical loadout using the four full capabilities of double banked SIMMs. It appears to me that the MoBo RAM is set up as a hobbled replacement for the first(second?) bank of the extra SIMM and that doing away with the MoBo DRAM ICs might free up those control lines for use on the unaddressable bank of the additional SIMM?
It's still and "under the board" PCB Hack, but what the heck!?! [}
] ]'>jt has the right of it.Do the Q605/LC 475 boot w/o the DRAM on the MoBo?
From what trag has said about the limitations of the second SIMM in the 605 and the 630, it makes me wonder if the Mobo RAM is excised these machines might be able to address the full theoretical loadout using the four full capabilities of double banked SIMMs. It appears to me that the MoBo RAM is set up as a hobbled replacement for the first(second?) bank of the extra SIMM and that doing away with the MoBo DRAM ICs might free up those control lines for use on the unaddressable bank of the additional SIMM?
It's still and "under the board" PCB Hack, but what the heck!?! [}
If you absolutely want to stick to chips which will fit in the 20 pin spots already on the logic boards, then yes, you are limited to 4MB total.
However, if you are willing to rig up additional connections, then you should be able to go up to 64 MB or possibly more. But this will be messy with wires and/or additional boards involved.
Case re-opened! From the bottom side. }
Continue discussion here if you would: Memory Addressing Questions
I'm already hip deep into the memory addressing issues of the IIsi, so I may as well head toward the deeper end of the pool and take on the Quadras 605 & 630 while I'm at it.
Great news, it turns out that only the Data lines are buffered by the 74LS245 quartet in order to buffer the Vampire VRAM/DRAM in Bank A.
We're getting there . . .
There's a fine old tradition of increasing memory capacity by piggybacking chips on each others backs like that. What the image doesn't show at first glance, is that it is not just a matter of soldering all the pins together, one to one. One must also get the additional higher address pin and apply some digital magic to some of the control lines to make it work. If you just piggyback directly, you simply have two chips trying to do identical work. They need a way of knowing that one set is used when an address pin that they can't see (not enough address pins) is '0' and the other is used when that address pin is '1'.
That said, it greatly reduces the amount of extra wiring, because most of the address pins, and all of the data pins are shared.
However, on the gripping hand, figuring out which control signals to modify can be a bear. You can't just hook up OE_ because that only handles reads. You can't assume that you can just modify RAS_ because the machine might use CAS before RAS refreshes, and that would mess with those. Without knowing the basics of how the machine is accessing RAM for both refresh and read/write operations, it gets tricky. I think that if you modify OE_ and WE_ both, then it should always work, but I'm not 100% certain about that.
That said, it greatly reduces the amount of extra wiring, because most of the address pins, and all of the data pins are shared.
However, on the gripping hand, figuring out which control signals to modify can be a bear. You can't just hook up OE_ because that only handles reads. You can't assume that you can just modify RAS_ because the machine might use CAS before RAS refreshes, and that would mess with those. Without knowing the basics of how the machine is accessing RAM for both refresh and read/write operations, it gets tricky. I think that if you modify OE_ and WE_ both, then it should always work, but I'm not 100% certain about that.
I didn't have time to post more than the pic before work today. You can see where one of the legs of the piggybacked IC is not connected to the matching leg of the lower IC if you look closely.
My thought is to look for a "double sided" 8MB 30-pin SIMM that has eight chips on each side of the type you're successfully using to net 4MB onto the MoBo.
Reverse engineer the addressing and control lines of such a SIMM will likely yield the information that will allow you to do the ugly Piggybacked RAM thing with some degree of confidence that it will work as an 8MB (onboard) RAM upgrade.
Putting a memory daughtercard underneath the MoBo is a far more elegant solution, capable of achieving vastly increased memory for very little money and less tedious wirework.
I've been watching this thread with great interest. I would love to double the amount of RAM my 475 can handle... 8-o
Sorry to hijack this thread a bit, but would this sort of thing work for a Classic II? It has 2MB onboard in the same style as this. Any chance it could be increased to 8MB (meaning 16MB total with the SIMM slots)?
Sorry to hijack this thread a bit, but would this sort of thing work for a Classic II? It has 2MB onboard in the same style as this. Any chance it could be increased to 8MB (meaning 16MB total with the SIMM slots)?
The Classic II is based on the LC II architecture (I think), so it stands to reason that the same limitations apply (both the C II and LC II are limited to 10 MB of RAM, for example).
Or maybe that was the Color Classic?
c
EDIT: No, I was right. According to Wikipedia, the Classic II architecture closely resembles that of the LC/LC II, and as such is subject to the same limitations and architectural design flaws.
Or maybe that was the Color Classic?
c
EDIT: No, I was right. According to Wikipedia, the Classic II architecture closely resembles that of the LC/LC II, and as such is subject to the same limitations and architectural design flaws.
I spent an hour or more downloading all the crap I could find relevant to this issue . . . for the morning. |)
A few highlights:
Dunno if this is the proper arrangement for the systems we're trying to hack, but to these crossed eyes it looks pretty good.
A couple of roads best left untraveled:
Step one:
dsc_0281.jpg[/attachment]
A few highlights:
Dunno if this is the proper arrangement for the systems we're trying to hack, but to these crossed eyes it looks pretty good.
A couple of roads best left untraveled:
Step one:
dsc_0281.jpg[/attachment]
Adding to my question regarding the Classic II, I just looked at a high res logic board image (since I'm too lazy to open mine) and it looks like it only has 4 RAM chips. Going by the part number shown (KM44C1000AJ- 8) it is unfortunately already using 1M x 4 ICs (which would make sense since it has 2MB(x8) onboard RAM).
Still, I wonder if it would get a speed boost using something faster than 80ns chips. The datasheets I found listed 70ns as an option for AJ, 60ns for the BJ revision, and up to 50ns for the DJ revision.
Those might also speed up the IIsi/475 as well.
Still, I wonder if it would get a speed boost using something faster than 80ns chips. The datasheets I found listed 70ns as an option for AJ, 60ns for the BJ revision, and up to 50ns for the DJ revision.
Those might also speed up the IIsi/475 as well.
Those are two different projects, either of which were probably prototypes done as proof of concept and determination of the traces needed for such a PCB. I'll be dong something very similar to the bottom one for each of my adapters for Bank B before worrying about actual PCBs. Such prototypes are effectively antenna farms, filling the entire case with nasty RFI or the whole room with the lid off. [}] ]'>
I've got pics of the prototype and final PCB in another, similar project. I'll dig 'em up to post here. The pic of the 72-pin SIMM with red wires attached might be from a similar project, dunno I'll see when i dig up the pics a/o bookmark.
Meanwhile, the block diagram above shows more of what I'm aiming to do in the Memory Addressing Questions thread . . .
found 'em! ;D
adapt_simm_16k.jpg[/attachment]
http://www.zxprojects.com/index.php/simm-adapter-for-replacing-lower-memory
This is an adaptation of good ole' DIP memory to a 30-pin SIMM, but it illustrates the process nicely. Bank A on the Q605/LC475 may be as badly lamed as on the IIsi and the DRAM on all these systems is SMT anyway. So this process would be fruitless at Bank A's location in the IIsi. So that's why I'm working on moving Bank A to a super-set of Bank B at that location for my project and suggesting an under the board PCB maximification adaptation project for the Q605/LC475that ought to work for the Q630 as well.
] ]'>I've got pics of the prototype and final PCB in another, similar project. I'll dig 'em up to post here. The pic of the 72-pin SIMM with red wires attached might be from a similar project, dunno I'll see when i dig up the pics a/o bookmark.
Meanwhile, the block diagram above shows more of what I'm aiming to do in the Memory Addressing Questions thread . . .
found 'em! ;D
adapt_simm_16k.jpg[/attachment]
http://www.zxprojects.com/index.php/simm-adapter-for-replacing-lower-memory
This is an adaptation of good ole' DIP memory to a 30-pin SIMM, but it illustrates the process nicely. Bank A on the Q605/LC475 may be as badly lamed as on the IIsi and the DRAM on all these systems is SMT anyway. So this process would be fruitless at Bank A's location in the IIsi. So that's why I'm working on moving Bank A to a super-set of Bank B at that location for my project and suggesting an under the board PCB maximification adaptation project for the Q605/LC475that ought to work for the Q630 as well.
The only stupid question is the one that doesn't get asked. 
Bank A and Bank B each have their own sets of address lines coming from adjacent pins on MDU in the IIsi/IIci and SE/30. Dunno how MEMCjr(?) is set up in the Q605/LC475. I don't have that schematic, but my guess would be that it's the same kind of deal. Buzz the connections to see if the MDU setup translates to the later Quadra Memory Controller.
You could almost certainly hotwire the additional address lines from the equivalent of MDU to Bank A. Figure out the rat's nest of control and addressing lines to run to a stack high enough of compatible pin count DRAM ICs on the existing pads on the MoBo in order to max out the memory config. But it would be one horribly fugly kluge mechanically, electrically, appearance wise, in terms of RFI transmission and one bear of a process to actually implement such a cluster-whatever. Even that still leaves you a SIMM slot short of maxing out the memory configuration overall.
I'm not crazy enough to take on that project, so it's a PCB adaptation under the board or nothing as far as I'm concerned.
Doubling onboard memory by cribbing the pin assignments from a sixteen compatible chip, double sided SIMM could be a doable double-stuffer hack. Has anyone got a SIMM like that to buzz the connections?
Bank A and Bank B each have their own sets of address lines coming from adjacent pins on MDU in the IIsi/IIci and SE/30. Dunno how MEMCjr(?) is set up in the Q605/LC475. I don't have that schematic, but my guess would be that it's the same kind of deal. Buzz the connections to see if the MDU setup translates to the later Quadra Memory Controller.
You could almost certainly hotwire the additional address lines from the equivalent of MDU to Bank A. Figure out the rat's nest of control and addressing lines to run to a stack high enough of compatible pin count DRAM ICs on the existing pads on the MoBo in order to max out the memory config. But it would be one horribly fugly kluge mechanically, electrically, appearance wise, in terms of RFI transmission and one bear of a process to actually implement such a cluster-whatever. Even that still leaves you a SIMM slot short of maxing out the memory configuration overall.
I'm not crazy enough to take on that project, so it's a PCB adaptation under the board or nothing as far as I'm concerned.
Doubling onboard memory by cribbing the pin assignments from a sixteen compatible chip, double sided SIMM could be a doable double-stuffer hack. Has anyone got a SIMM like that to buzz the connections?